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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 92/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 92 of 96
Table 132. T3CON MMR Bit Designations
Bit
Value
Description
15:9
These bits are reserved and should be written as
0s by user code.
8
Count up/down enable.
Set by user code to configure Timer3 to count up.
Cleared by user code to configure Timer3 to
count down.
7
Timer3 enable.
Set by user code to enable Timer3.
Cleared by user code to disable Timer3.
6
Timer3 operating mode.
Set by user code to configure Timer3 to operate
in periodic mode.
Cleared by user to configure Timer3 to operate in
free-running mode.
5
Watchdog timer mode enable.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
4
Secure clear bit.
Set by the user to use the secure clear option.
Cleared by the user to disable the secure clear
option by default.
3:2
Timer3 Clock(32.768 kHz) prescaler.
00
Source clock divide-by-1 (default).
01
Reserved.
10
Reserved.
11
Reserved.
1
Watchdog timer IRQ enable.
Set by user code to produce an IRQ instead of a
reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
0
PD_OFF.
Set by user code to stop Timer3 when the
peripherals are powered down via Bit 4 in the
POWCON MMR.
Cleared by user code to enable Timer3 when the
peripherals are powered down via Bit 4 in the
POWCON MMR.
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T3CLRI
to avoid a watchdog reset. The value is a sequence generated by
the 8-bit linear feedback shift register (LFSR) polynomial = X8 +
X6 + X5 + X + 1.
The initial value or seed is written to T3CLRI before entering
watchdog mode. After entering watchdog mode, a write to
T3CLRI must match this expected value. If it matches, the LFSR
is advanced to the next state when the counter reload happens.
If it fails to match the expected state, reset is immediately
generated, even if the count has not yet expired.
Because of the properties of the polynomial, do not use the
value, 0x00, as an initial seed. Value 0x00 is always guaranteed
to force an immediate reset. The value of the LFSR cannot be
read; it must be tracked/generated in software.
Example of a sequence:
1. Enter initial seed, 0xAA, in T3CLRI before starting Timer3
in watchdog mode.
2. Enter 0xAA in T3CLRI; Timer3 is reloaded.
3. Enter 0x37 in T3CLRI; Timer3 is reloaded.
4. Enter 0x6E in T3CLRI; Timer3 is reloaded.
5. Enter 0x66. 0xDC was expected; the watchdog resets
the chip.
Figure 40. 8-Bit LFSR
CLOCK
Q
D
4
Q
D
5
Q
D
3
Q
D
7
Q
D
6
Q
D
2
Q
D
1
Q
D
0
09492-
039
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