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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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Data Sheet
ADuC7121
Rev. B | Page 35 of 96
NONVOLATILE FLASH/EE MEMORY
FLASH/EE MEMORY OVERVIEW
The ADuC7121 incorporates Flash/EE memory technology on
chip to provide the user with nonvolatile, in circuit reprogram-
mable memory space.
Similar to EEPROM, flash memory can be programmed in system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
(and more correctly) referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes no volatility, in circuit program-
mability, high density, and low cost. Incorporated in the
ADuC7121, Flash/EE memory technology allows the user
to update program code space in circuit, without the need
to replace one time programmable (OTP) devices at remote
operating nodes.
FLASH/EE MEMORY
The ADuC7121 contains two 64 kB arrays of Flash/EE memory.
In the first block, the lower 62 kB is available to the user and the
upper 2 kB of this Flash/EE memory array program contain
permanently embedded firmware, allowing in circuit serial down-
load. The 2 kB of embedded firmware also contain a power-on
configuration routine that downloads factory calibrated coefficients
to the various calibrated peripherals (band gap references and
so forth). This 2 kB embedded firmware is hidden from user code.
It is not possible for the user to read, write, or erase this page.
In the second block, all 64 kB of Flash/EE memory are available
to the user.
The 126 kB of Flash/EE memory can be programmed in circuit
using the serial download mode or the JTAG mode.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the ADuC7121 are fully
qualified for two key Flash/EE memory characteristics:
Flash/EE memory cycling endurance and Flash/EE memory
data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as follows:
1. Initial page erase sequence
2. Read/verify sequence a single Flash/EE
3. Byte program sequence memory
4. Second read/verify sequence endurance cycle
In reliability qualification, every half word (16-bit wide) location
of the three pages (top, middle, and bottom) in the Flash/EE
memory is cycled 10,000 times from 0x0000 to 0xFFFF.
As indicated in the Specifications section, the Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 over the
industrial temperature range of –10° to +95°C. The results allow
the specification of a minimum endurance figure over a supply
temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. Note, too, that retention
lifetime, based on activation energy of 0.6 eV, derates with
Figure 26. Flash/EE Memory Data Retention
Serial Downloading (In-Circuit Programming)
The ADuC7121 facilitates code download via the I2C serial
port. The ADuC7121 enters serial download mode after a reset
or power cycle if the BM function of the P3.7/BM/PLAO[11]
pin is pulled low through an external 1 kΩ resistor. This is
combined with the state of Address 0x00014 in the flash. If this
address is 0xFFFFFFFF and BM is pulled low, the part enters
download mode; if this address contains any other value, user
code is executed. When in serial download mode, the user can
download code to the full 126 kB of Flash/EE memory while the
device is in circuit in its target application hardware. A PC serial
download executable and hardware dongle are provided as part of
the development system for serial downloads via the I2C port.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
FLASH/EE MEMORY SECURITY
The 126 kB of Flash/EE memory available to the user can be
read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR
protects the 126 kB from being read through JTAG and also in
I2C programming mode. The other 31 bits of this register protect
150
300
450
600
30
40
55
70
85
100
125
135
150
R
E
TE
N
TION
(
Y
ears)
0
09492-
025
JUNCTION TEMPERATURE (°C)
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