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型号： EVAL-ADUC7121QSPZ
厂商： Analog Devices Inc
文件页数： 25/96页
文件大小： 0K
描述： BOARD EVALUATION FOR ADUC7121
设计资源： ADUC7121 Gerber Files
ADUC7121 Schematic
标准包装： 1
系列： MicroConverter® ADuC7xxx
类型： MCU
适用于相关产品： ADUC7121
所含物品： 板，CD
Data Sheet
ADuC7121
Rev. B | Page 31 of 96
Table 30. ADCCP1 MMR Bit Designations
Bit
Value
Description
7:5
Reserved
4:0
Positive channel selection bits
00000
PADC0P
00001
PADC1P
00010
Reserved
00011
Reserved
00100
Reserved
00101
Reserved
00110
ADC4
00111
ADC5
01000
ADC6
01001
ADC7
01010
ADC8
01011
ADC9
01100
ADC10/AINCM
01101
Temperature sensor
01110
DVDD_IDAC0
01111
DVDD_IDAC1
10000
DVDD_IDAC2
10001
DVDD_IDAC3
10010
DVDD_IDAC4
10011
IOVDD_MON
10100
Reserved
10101
Reserved
10110
VREF
10111
AGND
Others
Reserved
1
ADC channel availability depends on part model.
Table 31. ADCCN1 MMR Bit Designations
Bit
Value
Description
7:5
Reserved
4:0
Negative channel selection bits
00000
PADC0N
00001
PADC1N
00010
Reserved
00011
Reserved
00100
Reserved
00101
Reserved
00110
ADC4
00111
ADC5
01000
ADC6
01001
ADC7
01010
ADC8
01011
ADC9
01100
ADC10/AINCM
01101
VREF
01110
AGND
01111
PGND
10000
IOGND
Others
Reserved
1
ADC channel availability depends on part model.
Table 32. ADCSTA MMR Bit Designations
Bit
Value
Description
0
1
Indicates that an ADC conversion is complete. It
is set automatically after an ADC conversion
completes.
0
Automatically cleared by reading the
ADCDAT MMR.
Table 33. ADCDAT MMR Bit Designations
Bit
Value
Description
27:16
Holds the ADC result (see Figure 16).
Table 34. ADCRST MMR Bit Designations
Bit
Value
Description
0
1
Set to 1 by the user to reset all the ADC
registers to their default values.
Table 35. PGA_GN MMR Bit Designations1
Bit
Value2
Description
11:6
N/A
Gain of PGA for PADC0 = 1 + 4 ×
(PGA_PADC0_GN/32).
5:0
N/A
Gain of PGA for PADC1 = 1 + 4 ×
(PGA_PADC1_GN/32).
1
PGA_PADC0_GN and PGA_PADC1_GN must be ≤ 32.
2
N/A means not applicable.
Table 36. ADCGN MMR Bit Designations
Bit
Value1
Description
11:6
N/A
These bits are reserved.
9:0
N/A
10-bit ADC gain calibration value for non-PGA
channels.
1
N/A means not applicable.
Table 37. ADCOF MMR Bit Designations
Bit
Value1
Description
15:10
N/A
These bits are reserved.
9:0
N/A
10-bit ADC offset calibration value.
1
N/A means not applicable.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge sampled input stage. This
architecture is described for the three different modes of
operation: differential, pseudo differential, and single-ended.
Differential Mode
The ADuC7121 contains a successive approximation ADC
based on two capacitive DACs. Figure 19 and Figure 20 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC comprises control logic, a SAR, and
two capacitive DACs. In Figure 19 (the acquisition phase), SW3
is closed and SW1 and SW2 are in Position A. The comparator
is held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
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