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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 46/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 50 of 96
Table 71. PWMCON1 MMR Bit Designations (Address = 0xFFFF0F80, Default Value = 0x0012)
Bit
Name
Description
15
Reserved
This bit is reserved.
14
SYNC
Enables PWM synchronization.
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on SYNC of the P0.3/MISO/PLAO[12]/SYNC pin.
Cleared by the user to ignore transitions on SYNC of the P0.3/MISO/PLAO[12]/SYNC pin.
13
PWM6INV
Set to 1 by the user to invert PWM6.
Cleared by the user to use PWM6 in normal mode.
12
PWM4NV
Set to 1 by the user to invert PWM4.
Cleared by the user to use PWM4 in normal mode.
11
PWM2INV
Set to 1 by the user to invert PWM2.
Cleared by the user to use PWM2 in normal mode.
10
PWMTRIP
Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an
interrupt is generated.
Cleared by the user to disable the PWMTRIP interrupt.
9
ENA
If HOFF = 0 and HMODE = 1. If HOFF = 1 and HMODE = 1, see Table 72. If not in H-Bridge mode, this bit has no effect.
Set to 1 by the user to enable PWM outputs.
Cleared by the user to disable PWM outputs.
8:6
PWMCP[2:0]
PWM clock prescaler bits. Sets the UCLK divider.
000 = UCLK divide-by-2.
001 = UCLK divide-by-4.
010 = UCLK divide-by-8.
011 = UCLK divide-by-16.
100 = UCLK divide-by-32.
101 = UCLK divide-by-64.
110 = UCLK divide-by-128.
111 = UCLK divide-by-256.
5
POINV
Set to 1 by the user to invert all PWM outputs.
Cleared by the user to use PWM outputs as normal.
4
HOFF
High-side off.
Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low.
Cleared by the user to use the PWM outputs as normal.
3
LCOMP
Load compare registers.
Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the
PWM timer from 0x00 to 0x01.
Cleared by the user to use the values previously stored in the internal compare registers.
2
DIR
Direction control.
Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low.
Cleared by the user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low.
1
HMODE
Enables H-bridge mode.
Set to 1 by the user to enable H-Bridge mode and Bits[5:2] of PWMCON1.
Cleared by the user to operate the PWMs in standard mode.
0
PWMEN
Set to 1 by the user to enable all PWM outputs.
Cleared by the user to disable all PWM outputs.
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