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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 85/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 86 of 96
TIMERS
The ADuC7121 has five general purpose timers/counters.
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4
The five timers in their normal mode of operation can be either
free-running or periodic.
In free-running mode, the counter decrements/increments
from the maximum/minimum value until zero scale/full scale
and starts again at the maximum/minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero scale/full
scale and starts again at the value stored in the load register.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero if counting down or full scale if counting
up. An IRQ can be cleared by writing any value to the clear
register of the particular timer (TxCLRI).
Table 123. Event Selection (ES) Numbers
ES
Interrupt No.
Name
00000
2
RTOS timer (Timer0)
00001
3
GP Timer0 (Timer1)
00010
4
Wake-up timer (Timer2)
00011
5
Watchdog timer (Timer3)
00100
6
GP Timer4 (Timer4)
00101
7
IDAC Fault IRQ
00110
8
Power supply monitor
00111
9
Undefined
01000
10
Flash Block 0
01001
11
Flash Block 1
01010
12
ADC
01011
13
UART
01100
14
SPI
01101
15
I2C0 master
01110
16
I2C0 slave
01111
17
I2C1 master
10000
18
I2C1 slave
10001
19
External IRQ0
HOUR:MINUTE:SECOND:1/128 FORMAT
To use the timer in hour:minute:second:hundredths format,
select the 32,768 kHz clock and prescaler of 256. The hundredths
field does not represent milliseconds but 1/128 of a second
(256/32,768). The bits representing the hour, minute, and
second are not consecutive in the register. This arrangement
applies to TxLD and TxVAL when using the
hour:minute:second:hundredths format as set in TxCON[5:4].
See Table 124 for additional details.
Table 124. Hour:Minnute:Second:Hundredths Format
Bit
Value
Description
31:24
0 to 23 or 0 to 255
Hours
23:22
0
Reserved
21:16
0 to 59
Minutes
15:14
0
Reserved
13.8
0 to 59
Seconds
7
0
Reserved
6:0
0 to 127
1/128 second
TIMER0—LIFETIME TIMER
Timer0 is a general-purpose, 48-bit count up, or a 16-bit count
up/down timer with a programmable prescaler. Timer0 is
clocked from the core clock, with a prescaler of 1, 16, 256, or
32,768. This gives a minimum resolution of 22 ns when the core
is operating at 41.78 MHz and with a prescaler of one. Timer0
can also be clocked from the undivided core clock, internal
32 kHz oscillator or external 32 kHz crystal.
In 48-bit mode, Timer0 counts up from zero. The current
counter value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or count down. A 16-bit
value can be written to T0LD that is loaded into the counter. The
current counter value can be read from T0VAL0. Timer0 has a
capture register (T0CAP) that can be triggered by a selected IRQ’s
source initial assertion. When triggered, the current timer value is
copied to T0CAP, and the timer keeps running. This feature can be
used to determine the assertion of an event with more accuracy
than by servicing an interrupt alone.
Timer0 reloads the value from T0LD either when TIMER0
overflows or immediately when T0ICLR is written.
Timer0 interface consists of six MMRs as listed in Table 125.
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