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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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Data Sheet
ADuC7121
Rev. B | Page 39 of 96
EXECUTION TIME FROM SRAM AND FLASH/EE
This section describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE), one
cycle to execute the instruction, and two cycles to retrieve the
32-bit data from Flash/EE. A control flow instruction, such as a
branch instruction, takes one cycle to fetch, but it also takes two
cycles to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 23 ns, execution from Flash/EE cannot be accomplished
in one cycle (as can be done from SRAM when the CD bit = 0). In
addition, some dead times are needed before accessing data for
any value of CD bits.
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In Thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter and
then four cycles are needed to fill the pipeline. A data processing
instruction involving only core registers does not require any
extra clock cycles, but if it involves data in Flash/EE, one
additional clock cycle is needed to decode the address of the
data and two additional cycles are needed to obtain the 32-bit
data from Flash/EE. An extra cycle must also be added before
fetching another instruction. Data transfer instructions are
more complex and are summarized in Table 46.
Table 46. Execution Cycles in ARM/Thumb Mode
Instructions
Fetch
Cycles
Dead
Time
Data Access
Dead
Time
LD
2/1
1
2
1
LDH
2/1
1
LDM/PUSH
2/1
N
2 × N
N
STR
2/1
1
2 × 20 s
1
STRH
2/1
1
20 s
1
STRM/POP
2/1
N
2 × N × 20 s
N
With 1 < N ≤ 16, N is the number of bytes of data to load or
store in the multiple load/store instruction. The SWAP instruction
combines an LD and STR instruction with only one fetch,
giving a total of eight cycles plus 40 μs.
RESET AND REMAP
The ARM exception vectors are situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020,
as shown in Figure 27.
Figure 27. Remap for Exception Execution
By default and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, facilitating execution of exception routines from SRAM
instead of from Flash/EE. This means exceptions are executed
twice as fast, with the exception being executed in ARM mode
(32 bits), and the SRAM being 32 bits wide instead of being
16-bit wide Flash/EE memory.
Remap Operation
When a reset occurs on the ADuC7121, execution starts auto-
matically in factory programmed internal configuration code.
This kernel is hidden and cannot be accessed by user code.
If the ADuC7121 is in normal mode (the P3.7/BM/PLAO[11] pin
is high), it executes the power-on configuration routine of the
kernel and then jumps to the Reset Vector Address 0x00000000 to
execute the user’s reset exception routine. Because the Flash/EE is
mirrored at the bottom of the memory array at reset, the reset
interrupt routine must always be written in Flash/EE.
The remap is performed from Flash/EE by setting Bit 0 of the
remap register. Precautions must be taken to execute this
command from Flash/EE (above Address 0x00080020) and not
from the bottom of the array because this, the defined memory
space, is replaced by the SRAM.
This operation is reversible: the Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the remap MMR.
Precaution must again be taken to execute the remap function
from outside the mirrored area. Any kind of reset remaps the
Flash/EE memory at the bottom of the array.
KERNEL
INTERRUPT
SERVICE ROUTINES
INTERRUPT
SERVICE ROUTINES
ARM EXCEPTION
VECTOR ADDRESSES
0x00000020
0x00041FFF
0x0008FFFF
0xFFFFFFFF
FLASH/EE
SRAM
MIRROR SPACE
0x00000000
0x00040000
0x00080000
09492-
026
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