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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 38/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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Data Sheet
ADuC7121
Rev. B | Page 43 of 96
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 30.
Figure 30. DAC Structure
As shown in Figure 30, the reference source for each DAC is
user-selectable in software. It can be either AVDD, VREF, or
EXT_REF. In 0 V-to-AVDD mode, the DAC output transfer
function spans from 0 V to the voltage at the AVDD pin. In 0 V-
to-EXT_REF mode, the DAC output transfer function spans
from 0 V to the voltage at the VREF_2.5 pin. In 0 V-to-VREF mode,
the DAC output transfer function spans from 0 V to the internal
2.5 V reference, VREF.
The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. This means that, when unloaded,
each output is capable of swinging to within less than 5 mV of
both AVDD and ground. Moreover, the linearity specification of the
DAC (when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except for Code 0 to Code 100,
and, in 0 V-to-AVDD mode only, Code 3995 to Code 4095.
Linearity degradation near ground and AVDD is caused by satu-
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is shown in Figure 31. The
dotted line in Figure 31 indicates the ideal transfer function, and
the solid line represents what the transfer function may look
like with endpoint nonlinearities due to saturation of the output
amplifier. Note that Figure 31 represents a transfer function in
0 V-to-AVDD mode only. In 0 V-to-VREF or 0 V-to-EXT_REF
modes (with VREF < AVDD or EXT_REF < AVDD), the lower
nonlinearity is similar. However, the upper portion of the
transfer function follows the ideal line right to the end (VREF in this
case, not AVDD), showing no signs of endpoint linearity errors.
Figure 31. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 31
worsen as a function of output loading. The ADuC7121 data sheet
specifications assume a 5 kΩ resistive load to ground at the DAC
output. As the output is forced to source or sink more current,
the nonlinear regions at the top or bottom (respectively) of
Figure 31 become larger. With larger current demands, this can
significantly limit output voltage swing.
LDO (LOW DROPOUT REGULATOR)
The ADuC7121 contains an integrated LDO, which generates
the core supply voltage (DVDD) of approximately 2.6 V from
the IOVDD supply. As the LDO is driven from IOVDD, the
IOVDD supply voltage needs to be greater than 2.7 V.
An external compensation capacitor (CT) of 0.47 μF with low
ESR must be placed very close to each of the DVDD pins. This
capacitor also acts as a storage tank of charge, and supplies an
instantaneous charge required by the core, particularly at the
positive edge of the core clock (HCLK).
The DVDD voltage generated by the LDO is solely for providing
a supply for the ADuC7121. Therefore, users should not use a
DVDD pin as the power supply pin for any other chip. In
addition, it is recommended that the IOVDD has excellent
power supply decoupling to help improve line regulation
performance of the LDO.
The DVDD pin has no reverse battery, current limit, or thermal
shutdown protection; therefore, it is essential that users of the
ADuC7121 do not short this pin to ground at any time during
normal operation or during board manufacture.
CURRENT OUTPUT DACs (IDAC)
The ADuC7121 provides five current output digital-to-analog
converters (DACs). The current sources (five current DACs)
feature low noise and low drift high-side current output with
11-bit resolution. The five IDACs are as follows: IDAC0 with
250 mA full-scale (FS) output, IDAC1 with 200 mA FS output,
IDAC2 with 45 mA FS output, IDAC3 with 80 mA FS output,
and IDAC4 with 20 mA FS output.
09
49
2-
0
29
R
DAC0
VREF
AVDD
EXT_REF
09
49
2-
0
30
AVDD
AVDD – 100mV
100mV
0x00000000
0x0FFF0000
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