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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 89/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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Data Sheet
ADuC7121
Rev. B | Page 9 of 96
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Digital Power Supply Current
IOVDD Current in Normal Mode
Code executing from Flash/EE
7
mA
CD = 7
11
mA
CD = 3
30
40
mA
CD = 0 (41.78 MHz clock)
25
mA
CD = 0 (41.78 MHz clock)
100
A
TA = 25°C
Additional Power Supply Currents
ADC
2.7
mA
@1 MSPS
IDAC
21
mA
All current DACs (IDACs) on
DAC
250
A
per VDAC
ESD TESTS
2.5 V reference, TA = 25°C
HBM Passed Up to
4
kV
FICDM Passed Up to
0.5
kV
1
All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2
Apply to all ADC input channels.
3
Measured using the factory set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4
Not production tested but supported by design and/or characterization data on production release.
5
Measured using the factory set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 24. Based on external ADC
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the ADC section).
6
The input signal can be centered on any dc common-mode voltage (VCM) provided that this value is within the ADC voltage input range specified.
7
VREF calibration and trimming are performed under the following conditions: the core is operating in normal mode CD = 0, the ADC is on, the current DACs are on, and
all VDACs are on. VREF accuracy may vary under other operating conditions.
8
The PVDD_IDAC0 pad voltage must be at least 300 mV greater than the IDAC0 pad voltage. These voltages are measured via the PVDD0 and IDAC0 channels of the
ADC. This allows the IDAC0 pin to be pulled up to 1.7 V provided that this 300 mV differential voltage is maintained between the pads. This may require the
PVDD_IDAC0 being supplied with a voltage greater than 2.0 V. The 2.1 V maximum PVDD_IDACx rating must not be exceeded.
9
DAC linearity is calculated using a reduced code range of 100 to 3995.
10
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
11
Die temperature.
12
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at 40°C, +25°C, +85°C, and +125°C.
13
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
14
Test carried out with a maximum of eight I/Os set to a low output level.
15
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode using a 3.6 V supply, pause mode
using a 3.6 V supply, and sleep mode using 3.6 V supply.
16
IOVDD power supply current increases typically by 2 mA during a Flash/EE erase cycle.
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