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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 91/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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Data Sheet
ADuC7121
Rev. B | Page 91 of 96
TIMER3—WATCHDOG TIMER
Figure 39. Timer3 Block Diagram
Timer3 has two modes of operation: normal mode and watchdog
mode. The watchdog timer is used to recover from an illegal
software state. When enabled, it requires periodic servicing to
prevent it from forcing a reset of the processor.
Timer3 reloads the value from T3LD either when Timer3
overflows or immediately when T3CLRI is written.
Normal Mode
The Timer3 in normal mode is identical to Timer0 in 16-bit
mode of operation, except for the clock source. The clock source
is the 32.768 kHz oscillator and can be scaled by a factor of 1,
16, or 256. Timer3 also features a capture facility that allows
capture of the current timer value if the Timer2 interrupt is
enabled via IRQEN[5].
Watchdog Mode
Watchdog mode is entered by setting T3CON[5]. Timer3 decre-
ments from the timeout value present in the T3LD register until
0. The maximum timeout is 512 seconds, using the maximum
prescaler divide-by-256 and full scale in T3LD.
User software should only configure a minimum timeout
period of 30 milliseconds. This is to avoid any conflict with
Flash/EE memory page erase cycles, requiring 20 ms to
complete a single page erase cycle and kernel execution.
If T3VAL reaches 0, a reset or an interrupt occurs, depending
on T3CON[1]. To avoid a reset or an interrupt event, any value
must be written to T3ICLR before T3VAL reaches zero. This
reloads the counter with T3LD and begins a new timeout
period.
Once watchdog mode is entered, T3LD and T3CON are write
protected. These two registers cannot be modified until a power-
on reset event resets the watchdog timer. After any other reset
event, the watchdog timer continues to count. The watchdog
timer should be configured in the initial lines of user code to
avoid an infinite loop of watchdog resets.
Timer3 is automatically halted during JTAG debug access and
only recommences counting once JTAG has relinquished control
of the ARM7 core. By default, Timer3 continues to count during
power-down. This can be disabled by setting Bit 0 in T3CON. It
is recommended that the default value is used, that is, the
watchdog timer continues to count during power-down.
Timer3 Interface
Timer3 interface consists of four MMRS as shown in Table 131.
Table 131. Timer3 Interface Registers
Register
Description
T3CON
The configuration MMR.
T3LD
6-bit register (Bit 0 to Bit15); holds 16-bit unsigned
integers.
T3VAL
6-bit register (Bit 0 to Bit 15); holds 16-bit unsigned
integers. This register is read only.
T3CLRI
8-bit register. Writing any value to this register clears
the Timer3 interrupt in normal mode or resets a new
timeout period in watchdog mode.
Timer3 Load Register
This 16-bit MMR holds the Timer3 reload value.
Name:
T3LD
Address:
0xFFFF0360
Default value: 0x3BF8
Access:
Read and write
Timer3 Value Register
This 16-bit, read-only MMR holds the current Timer3 count value.
Name:
T3VAL
Address:
0xFFFF0364
Default value: 0x3BF8
Access:
Read only
Timer3 Clear Register
This 8-bit, write-only MMR is written (with any value) by user
code to refresh (reload) Timer3 in watchdog mode to prevent a
watchdog timer reset event.
Name:
T3CLRI
Address:
0xFFFF036C
Default value: 0x0000
Access:
Write only
Timer3 Control Register
The 16-bit MMR configures the mode of operation of Timer3
and is described in detail in Table 132.
Name:
T3CON
Address:
0xFFFF0368
Default value: 0x0000
Access:
Read and write one time only
TIMER3IRQ
16-BIT LOAD
16-BIT
UP/DOWN
COUNTER
TIMER3 VALUE
PRESCALER
1, 16, OR 256
WATCHDOG
RESET
LOW POWER
32.768kHz
09492-
038
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