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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 28 of 96
1/2 LSB, 3/2 LSBs, 5/2 LSBs, …, FS 3/2 LSBs). The ideal input/
output transfer characteristic is shown in Figure 14.
Figure 14. ADC Transfer Function in Differential Mode
PADC0x/PADC1x Pins
The PADC0x and PADC1x pins are differential input channels
to the ADC that each have a programmable gain amplifier
(PGA ) on their front ends.
An external precision resistor converts the current to voltage and
the PGA then amplifies this voltage signal with gain up to 5 by
32 steps. The intention is to compensate the variation of the
detector diode responsivity and normalize optical power read
by the ADC. The external resistor is assumed 0.1% accuracy,
5 ppm. A 1 nF capacitor is shunted with the resistor to suppress
wideband noise. Select the resistor value such that the full-scale
voltage developed on the resistor is less than AVDD 1.2 V, or
typically 1.8 V.
The PGA is designed to handle 10 mV minimum input. To
minimize noise, bypass the ADC input buffer.
PADC0N is driven by a buffer to 0.15 V to keep the PGA from
saturation when the input current drops to zero. The buffer can
be disabled by setting the ADCCON Bit 14 so that the PADC0N
pin can be connected to the ground plane as well. This is the
same for the PADC1N pin.
The ADC needs to be placed in pseudo differential mode and
assumes that the negative input is close to ground.
All of the controls are independently set through register bits
for giving maximum flexibility to the user. Typically, users need
to take the following steps:
1.
Select PADCxP and PADCxN in the ADCCP and ADCCN
registers.
2.
Optionally, bypass the ADC input buffers in
ADCCON[15:14].
3.
Set the proper gain value for the PGA in PGA_GN.
4.
Set the ADC to pseudo differential mode in
ADCCON[4:3].
5.
Start the conversion.
Figure 15. PADC0x/PADC1x ADC Input
Other Input Channels
ADuC7121 contains seven extra ADC input pins. These pins
can also be configured as differential input pairs or single-ended
inputs, or pseudo differential inputs. The buffer and ADC are
configured independently from the input channel selection. Note
that the input range of the ADC input buffer is from 0.15 V to
AVDD 0.15 V; if the input signal range exceeds this range, the
input buffer must be bypassed.
The ADuC7121 provides two pins for each thermistor input.
The negative input removes the error of the ground difference.
When selecting the thermistor input, always bypass the negative
side buffer to ensure that the amplifier is not saturated. Configure
the ADC to work in positive pseudo differential mode.
Besides these external inputs, the ADC can also select internal
inputs to monitor three power supplies: IOVDD, PVDD_IDAC0,
and PVDD_IDAC1. The voltage of the five IDAC outputs can
also be monitored by the ADC by selecting the required
channel in Register ADCCP. These internal signals are single-
ended and can select AGND/PGND/IOGND as the negative
input of the ADC via the ADCCN register.
Note that when monitoring IDAC outputs or PVDD_IDAC0,
PVDD_IDAC1, or IOVDD_MON, the buffer must be enabled
to isolate interference from ADC sampling.
An on-chip diode can also be selected to provide chip temperature
monitoring. The ADC can also select VREF and AGND as inputs
for calibration purposes.
PGA and Input Buffer
The PGA is a one stage, positive gain amplifier that is able to
accept input from 0.1 V to AVDD 1.2 V, and the output swing
should be at least 2.5 V. The gain of the PGA is from 1 to 5 with
32 linear steps. The PGA cannot be bypassed for the PADC0x
and PADC1x channels.
The input level for PGA is limited to a maximum value of
AVDD 1.2 V and minimum value of 0.1 V to ensure that the
O
UT
P
UT
CO
DE
VOLTAGE INPUT (VIN+ – VIN–)
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0001
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
–VREF + 1LSB
+VREF – 1LSB
0LSB
1LSB =
2 × VREF
4096
SIGN
BIT
09
49
2-
0
14
PADC0_P
PADC0_N
SAR
ADC
EXTERNAL
09
49
2-
04
0
MU
X
0.15V
0.1%,
5ppm
1nF
GAIN SET BY
PGA_GN[11:6]
PADC1_P
PADC1_N
0.15V
0.1%,
5ppm
1nF
GAIN SET BY
PGA_GN[5:0]
MISCELLANEOUS
OTHER
BUFFER BYPASS
SWITCH
ADCCON[15]
BUFFER
BYPASS
SWITCH
ADCCON[14]
VREF_EXT
VREF_INT
TO
MCU
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