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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 65/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 68 of 96
I2C Slave Status Registers
These 16-bit MMRs are the I2C status registers in slave mode.
Name:
I2C0SSTA, I2C1SSTA
Address:
0xFFFF08AC, 0xFFFF092C
Default value:
0x0000, 0x0000
Access:
Read and write
Table 97. I2CxSSTA MMR Bit Designations
Bit
Name
Description
15
Reserved bit.
14
I2CSTA
This bit is set to 1 if:
A start condition followed by a matching address is detected.
A start byte (0x01) is received.
General calls are enabled and a general call code of (0x00) is received.
This bit is cleared on receiving a stop condition.
13
I2CREPS
This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition.
12:11
I2CID[1:0]
I2C address matching register. These bits indicate which I2CxIDx register matches the received address.
[00] = Received address matches I2CxID0.
[01] = Received address matches I2CxID1.
[10] = Received address matches I2CxID2.
[11] = Received address matches I2CxID3.
10
I2CSS
I2C stop condition after start detected bit.
This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI
bit in I2CxSCTL is set, an interrupt is generated.
This bit is cleared by reading this register.
9:8
I2CGCID[1:0]
I2C general call ID bits.
[00] = no general call received.
[01] = general call reset and program address.
[10] = general program address.
[11] = general call matching alternative ID.
Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCTL. Note that these bits are not cleared by a general call
reset command.
7
I2CGC
I2C general call status bit.
This bit is set to 1 if the slave receives a general call command of any type. If the command received was a reset
command, all registers return to their default state. If the command received was a hardware general call, the Rx
FIFO holds the second byte of the command and this can be compared with the I2CxALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCTL.
6
I2CSBUSY
I2C slave busy status bit.
Set to 1 when the slave receives a start condition.
Cleared by hardware under the following conditions:
The received address does not match any of the I2CxIDx registers.
The slave device receives a stop condition.
A repeated start address does not match any of the I2CxIDx registers.
5
I2CSNA
I2C slave no acknowledge data bit.
This bit sets to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted under the
following conditions:
If no acknowledge was returned because there was no data in the Tx FIFO.
If the I2CNACKEN bit was set in the I2CxSCTL register.
This bit is cleared in all other conditions.
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