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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 72/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 74 of 96
Table 100. SPICON MMR Bit Designations
Bit
Name
Description
15:14
SPIMDE
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
[00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been
received into the FIFO.
[01] = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been
received into the FIFO.
[10] = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have
been received into the FIFO.
[11] = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or four
bytes present.
13
SPITFLH
SPI Tx FIFO flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit
is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit. Any writes to the
Tx FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
12
SPIRFLH
SPI Rx FIFO flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit
is set, all incoming data is ignored and no interrupts are generated. If this bit is set and SPITMDE = 0, a read of the Rx
FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
11
SPICONT
Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the Tx register. The P0.5/CS/PLAI[10]/ADCCONVST pin is asserted and remains asserted for the duration of each 8-bit serial
transfer until Tx is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle.
10
SPILP
Loopback enable bit.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to be in normal mode.
9
SPIOEN
Slave MISO output enable bit.
Set this bit for normal operation of MISO.
Clear this bit to disable the output driver on the MISO pin. The MISO pin is open drain when this bit is clear.
8
SPIROW
SPIRX overflow overwrite enable.
Set by the user, the valid data in the Rx register is overwritten by the new serial byte that is received.
Cleared by the user, the new serial byte that is received is discarded.
7
SPIZEN
SPI transmits zeros when Tx FIFO is empty.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.
6
SPITMDE
SPI transfer and interrupt mode.
Set by the user to initiate a transfer with a write to the SPITX register. Interrupt occurs only when Tx is empty.
Cleared by the user to initiate a transfer with a read of the SPIRX register. Interrupt occurs only when Rx is full.
5
SPILF
LSB first transfer enable bit.
Set by the user, the LSB is transmitted first.
Cleared by the user, the MSB is transmitted first.
4
SPIWOM
SPI wired or mode enable bit.
Set to 1 to enable open-drain data output enable. External pull-ups are required on data output pins.
Clear for normal output levels.
3
SPICPO
Serial clock polarity mode bit.
Set by the user, the serial clock idles high.
Cleared by the user, the serial clock idles low.
2
SPICPH
Serial clock phase mode bit.
Set by the user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user, the serial clock pulses at the end of each serial bit transfer.
1
SPIMEN
Master mode enable bit.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
0
SPIEN
SPI enable bit.
Set by the user to enable the SPI.
Cleared by the user to disable the SPI.
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