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参数资料
型号： EVAL-ADUC7121QSPZ
厂商： Analog Devices Inc
文件页数： 80/96页
文件大小： 0K
描述： BOARD EVALUATION FOR ADUC7121
设计资源： ADUC7121 Gerber Files
ADUC7121 Schematic
标准包装： 1
系列： MicroConverter® ADuC7xxx
类型： MCU
适用于相关产品： ADUC7121
所含物品： 板，CD
Data Sheet
ADuC7121
Rev. B | Page 81 of 96
FIQCLR
FIQCLR is a write-only register that allows the FIQEN register
to clear to mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the FIQEN register without
affecting the remaining bits. The pair of registers, FIQEN and
FIQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
Use this register to disable an interrupt source only when:
The device is in the interrupt sources interrupt service
routine.
The peripheral is temporarily disabled by its own control
register.
Do not use this register to disable an FIQ source if that FIQ
source has an interrupt pending or could have an interrupt
pending.
FIQCLR Register
Name:
FIQCLR
Address:
0xFFFF010C
Default value:
0x00000000
Access:
Write only
FIQSTA
FIQSTA is a read-only register that provides the current enabled
FIQ source status (effectively a logic AND of the FIQSIG and
FIQEN bits). When set to 1, that source generates an active FIQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
FIQSTA Register
Name:
FIQSTA
Address:
0xFFFF0100
Default value:
0x00000000
Access:
Read only
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 111. This MMR allows the control of a
programmed source interrupt.
Table 111. SWICFG MMR Bit Designations
Bit
Description
31:3
Reserved.
2
Programmed Interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
1
Programmed Interrupt IRQ1. Setting or clearing this bit
corresponds to setting or clearing Bit 1 of IRQSTA and
IRQSIG.
0
Reserved.
Any interrupt signal must be active for at least the minimum
interrupt latency time, to be detected by the interrupt controller
and to be detected by the user in the IRQSTA/FIQSTA register.
Figure 38. Interrupt Structure
Vectored Interrupt Controller (VIC)
The ADuC7121 incorporates an enhanced interrupt control
system or vectored interrupt controller. The vectored interrupt
controller for IRQ interrupt sources is enabled by setting Bit 0
of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables
the vectored interrupt controller for the FIQ interrupt sources.
The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:
Vectored interrupts—allows a user to define separate
interrupt service routine addresses for every interrupt
source. This is achieved by using the IRQBASE and
IRQVEC registers.
IRQ/FIQ interrupts—can be nested up to eight levels
depending on the priority settings. An FIQ still has a higher
priority than an IRQ. Therefore, if the VIC is enabled for both
the FIQ and IRQ and prioritization is maximized, it is
possible to have 16 separate interrupt levels.
Programmable interrupt priorities—using the IRQP0 to
IRQP3 registers, an interrupt source can be assigned an
interrupt priority level value between 0 and 7.
09
49
2-
03
7
POINTER TO
FUNCTION
(IRQVEC)
IRQ_SOURCE
FIQ_SOURCE
PROGRAMMABLE PRIORITY
PER INTERRUPT (IRQP0/IRQP1/IRQP2)
INTERNAL
ARBITER
LOGIC
INTERRUPT VECTOR
BIT 31 TO
BIT 23
UNUSED
BIT 1 TO
BIT 0
LSB
BIT 22 TO BIT 7
(IRQBASE)
BIT 6 TO
BIT 2
HIGHEST
PRIORITY
ACTIVE IRQ
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