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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 41/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 46 of 96
Table 61. IDAC Bandwidth Registers (Default Value = 0x00,
Read and Write Access)
Name
Address
IDAC0BW
0xFFFF0708
IDAC1BW
0xFFFF0714
IDAC2BW
0xFFFF0720
IDAC3BW
0xFFFF072C
IDAC4BW
0xFFFF0738
Table 62. IDACxBW MMR Bit Designations
Bit
Name
Value
Description
7:4
Reserved
The user sets these bits to 0.
3:0
BW
Bandwidth control bits. Defines the
3 dB bandwidth of the RC low-pass
filter, assuming a 0.01 μF capacitor
on the CDAMP_IDACx pins of the
IDACx.
000
100 kHz.
001
28.7 kHz.
010
15 kHz.
011
7.8 kHz.
100
4 kHz.
101
2.2 kHz.
110
1.2 kHz.
Others
Not defined.
Table 63. IDAC Status Register (Default Value = 0x00, Read
and Write Access)
Name
Address (Hex)
IDACSTA
0xFFFF0740
Table 64. IDACSTA MMR Bit Designations
Bit
Value
Name
Description
7:2
Reserved
These bits are set to 0 by the user.
1
0
TSHUT
Thermal shutdown error status bit.
Set to 1 by the core indicating a
thermal shutdown event.
Set to 0 by the core indicating the
IDACs are within operating
temperature.
0
Reserved
Reserved.
OSCILLATOR AND PLL—POWER CONTROL
The ADuC7121 integrates a 32.768 kHz oscillator, a clock divider,
and a PLL. The PLL locks onto a multiple (1275) of the internal
oscillator to provide a stable 41.78 MHz clock for the system.
The core can operate at this frequency, or at binary submultiples
of it, to allow for power saving. The default core clock is the PLL
clock divided by 8 (CD = 3) or 5.2 MHz. The core clock frequency
can be output on the XCLK pin as described in Figure 33. Note
that when the XCLK pin is used to output the core clock, the
output signal is not buffered and is not suitable for use as a
clock source to an external device without an external buffer.
A power-down mode is available on the ADuC7121.
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs, PLLCON (see Table 67) and
POWCON (see Table 68). PLLCON controls the operating
mode of the clock system, and POWCON controls the core
clock frequency and the power-down mode.
Figure 33. Clocking System
External Crystal Selection
To switch to an external crystal, use the following procedure:
1. Enable the Timer2 interrupt and configure it for a timeout
period of >120 s.
2. Follow the write sequence to the PLLCON register, setting
the MDCLK bits to 01 and clearing the OSEL bit.
3. Force the part into nap mode by writing the correct write
sequence to the POWCON register.
4. When the part is interrupted from nap mode by the Timer2
interrupt source, the clock source has switched to the
external clock.
In noisy environments, noise can couple to the external crystal
pins, and PLL may lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is serviced only when the lock is restored.
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA register can determine if the
reset came from the watchdog timer.
09492-
032
AT POWER-UP
41.78MHz
OCLK 32.768kHz
WATCHDOG
TIMER
INT. 32kHz1
OSCILLATOR
CRYSTAL
OSCILLATOR
TIMERS
MDCLK
HCLK
PLL
CORE
I2C
UCLK
ANALOG
PERIPHERALS
/2CD
CD
XTALO
XTALI
P1.4/XCLK
P1.4/ECLK
132.768kHz ±3%
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