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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 90/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 90 of 96
TIMER2—WAKE-UP TIMER
Timer2 is a 32-bit wake-up timer, count down or count up, with
a programmable prescaler. The prescaler is clocked directly from
one of four clock sources, namely, the core clock (default selection),
the internal 32.768 kHz oscillator, the external 32.768 kHz
watch crystal, or the PLL undivided clock. The selected clock
source can be scaled by a factor of 1, 16, 256, or 32,768. The
wake-up timer continues to run when the core clock is disabled.
This gives a minimum resolution of 22 ns when the core is
operating at 41.78 MHz and with a prescaler of 1. Capture of
the current timer value is enabled if the Timer2 interrupt is
enabled via IRQEN[4].
The counter can be formatted as a plain 32-bit value or as
Hours:Minutes:Seconds:Hundredths.
Timer2 reloads the value from T2LD either when Timer2 over-
flows or immediately when T2CLRI is written. The Timer2
interface consists of four MMRs, as shown in Table 129.
Table 129. Timer2 Interface Registers
Register
Description
T2LD
32-bit register. Holds 32-bit unsigned integers.
T2VAL
32-bit register. Holds 32-bit unsigned integers.
This register is read only.
T2CLRI
8-bit register. Writing any value to this register clears
the Timer2 interrupt.
T2CON
Configuration MMR.
Timer2 Load Registers
T2LD is a 32-bit register, which holds the 32 bit value that is
loaded into the counter.
Name:
T2LD
Address:
0xFFFF0340
Default value: 0x00000000
Access:
Read and write
Timer2 Clear Register
This 8-bit write-only MMR is written (with any value) by the
user code to refresh (reload) Timer2.
Name:
T2CLRI
Address:
0xFFFF034C
Default value: 0x00
Access:
Write only
Timer2 Value Register
T2VAL is a 32-bit register that holds the current value of Timer2.
Name:
T2VAL
Address:
0xFFFF0344
Default value: 0x00000000
Access:
Read only
Timer2 Control Register
This 32-bit MMR configures the mode of operation for Timer2.
Name:
T2CON
Address:
0xFFFF0348
Default value: 0x00000000
Access:
Read and write
Table 130. T2CON MMR Bit Designations
Bit
Value
Description
31:11
Reserved.
10:9
Clock source select.
00
Internal 32.768 kHz oscillator (default).
01
Core clock.
10
External 32.768kHz watch crystal.
11
UCLK.
8
Count up.
Set by the user for Timer2 to count up.
Cleared by the user for Timer2 to count down
(default).
7
Timer2 enable bit.
Set by the user to enable Timer2.
Cleared by the user to disable Timer2 (default).
6
Timer2 mode.
Set by the user to operate in periodic mode.
Cleared by the user to operate in free-running
mode (default).
5:4
Format.
00
Binary (default).
01
Reserved.
10
Hr:Min:Sec:Hundredths: 23 hours to 0 hour.
11
Hr:Min:Sec:Hundredths: 255 hours to 0 hour.
3:0
Prescaler.
0000
Source clock divide-by-1 (default).
0100
Source clock divide-by-16.
1000
Source clock divide-by-256. (Use this setting in
conjunction with Timer2 Format 1,0 and
Format 1,1.)
1111
Source clock divide-by-32,768.
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