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| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 61/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 64 of 96
I2C Master Status Register
This 16-bit MMR is I2C status register in master mode.
Name:
I2C0MSTA, I2C1MSTA
Address:
0xFFFF0884, 0xFFFF0904
Default value:
0x0000, 0x0000
Access:
Read only
Table 90 I2CxMSTA MMR Bit Designations
Bit
Name
Description
15:11
Reserved. These bits are reserved.
10
I2CBBUSY
I2C bus busy status bit.
This bit is set to 1 when a start condition is detected on the I2C bus.
This bit is cleared when a stop condition is detected on the bus.
9
I2CMRxFO
Master receiver (Rx) FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
8
I2CMTC
I2C transmission complete status bit.
This bit is set to 1 when a transmission is complete between the master and the slave with which it was
communicating. If the I2CMCENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMTC bit is set.
Clear this interrupt source.
7
I2CMNA
I2C master no acknowledge data bit.
This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write transfer. If
the I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMNA bit is set.
This bit is cleared in all other conditions.
6
I2CMBUSY
I2C master busy status bit.
Set to 1 when the master is busy processing a transaction.
Cleared if the master is ready or if another master device has control of the bus.
5
I2CAL
I2C arbitration lost status bit.
This bit is set to 1 when the I2C master is unsuccessful in gaining control of the I2C bus. If the I2CALENI bit in
I2CxMCTL is set, an interrupt is generated when the I2CAL bit is set.
This bit is cleared in all other conditions.
4
I2CMNA
I2C master no acknowledge address bit.
This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If the
I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMNA bit is set.
This bit is cleared in all other conditions.
3
I2CMRXQ
I2C master receive request bit.
This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCTL is set, an interrupt is generated.
This bit is cleared in all other conditions.
2
I2CMTXQ
I2C master transmit request bit.
This bit goes high if the transmitter (Tx) FIFO is empty or only contains one byte and the master has transmitted an
address + write. If the I2CMTENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMTXQ bit is set.
This bit is cleared in all other conditions.
1:0
I2CMTFSTA
I2C master Tx FIFO status bits.
00 = I2C master Tx FIFO empty.
01 = one byte in master Tx FIFO.
10 = one byte in master Tx FIFO.
11 = I2C master Tx FIFO full.
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