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参数资料
| 型号： | EVAL-ADUC7121QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 设计资源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7121 |
| 所含物品： | 板，CD |
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Data Sheet
ADuC7121
Rev. B | Page 23 of 96
MEMORY ORGANIZATION
The ADuC7121 incorporates three separate blocks of memory:
8 kB of SRAM and two 64 kB of on-chip Flash/EE memory.
There are 126 kB of on-chip Flash/EE memory available to the
user, and the remaining 2 kB are reserved for the factory-
configured boot page. These two blocks are mapped as shown
Note that by default, after a reset, the Flash/EE memory is mirrored
at Address 0x00000000. It is possible to remap the SRAM at
Address 0x00000000 by clearing Bit 0 of the REMAP MMR.
This remap function is described in more detail in the Flash/EE
Memory section.
Figure 9. Physical Memory Map
MEMORY ACCESS
The ARM7 core sees memory as a linear array of 232 byte
locations where the different blocks of memory are mapped as
outlined in Figure 9.
The ADuC7121 memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte is located in the
highest byte address.
Figure 10. Little Endian Format
FLASH/EE MEMORY
The 128 kB of Flash/EE are organized as two banks of 32k × 16
bits. The first block, Block 0, controls flash, starting at
Address 0x80000 and finishing at Address 0x90000. In the first
block, 31k × 16 bits is user space and 1k × 16 bits is reserved for
the factory configured boot page. The page size of this Flash/EE
memory is 512 bytes.
The second block, Block 1, controls flash, starting at
Address 0x90000 and finishing at Address 0x9F700. The second
64 kB block is arranged in 32k × 16 bits, all of which is available
as user space.
The 126 kB of Flash/EE are available to the user as code and
nonvolatile data memory. There is no distinction between data
and program because ARM code shares the same space. The real
width of the Flash/EE memory is 16 bits, meaning that in ARM
mode (32-bit instruction), two accesses to the Flash/EE are neces-
sary for each instruction fetch. Therefore, it is recommended that
Thumb mode be used when executing from Flash/EE memory
for optimum access speed. The maximum access speed for the
Flash/EE memory is 41.78 MHz in Thumb mode and 20.89 MHz
in full ARM mode (see the Execution Time from SRAM and
FLASH/EE section).
SRAM
The 8 kB of SRAM are available to the user, organized as 2k ×
32 bits, that is, 2k words. ARM code can run directly from
SRAM at 41.78 MHz, given that the SRAM array is configured
as a 32-bit wide memory array (see the Execution Time from
SRAM and FLASH/EE section).
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers, except the core registers, reside
in the MMR area. All shaded locations shown in Figure 11 are
unoccupied or reserved locations and should not be accessed by
user software. Table 10 through Table 27 provide the complete
MMR memory maps.
The access time reading or writing an MMR depends on the
advanced microcontroller bus architecture (AMBA) bus used
to access the peripheral. The processor has two AMBA buses:
advanced high performance bus (AHB) used for system modules
and advanced peripheral bus (APB) used for a lower performance
peripheral. Access to the AHB is one cycle, and access to the
APB is two cycles. All peripherals on the ADuC7121 are on the
APB except the Flash/EE memory and the GPIOs.
RESERVED
0x00080000
FLASH/EE
RESERVED
0x00041FFF
0x00040000
SRAM
0xFFFF0000
0xFFFFFFFF
MMRs
0x0001FFFF
0x00000000
0x0009F800
RESERVED
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
09492-
009
BIT 31
BYTE 2
A
6
2
.
BYTE 3
B
7
3
.
BYTE 1
9
5
1
.
BYTE 0
8
4
0
.
BIT 0
32 BITS
0xFFFFFFFF
0x00000004
0x00000000
09492-
010
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