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参数资料
型号： EVAL-ADUC7124QSPZ
厂商： Analog Devices Inc
文件页数： 72/108页
文件大小： 0K
描述： BOARD EVALUATION FOR ADUC7124
设计资源： EVAL-ADUC7124 Schematic
ADUC7124 Eval Brd Gerber Files
标准包装： 1
系列： MicroConverter® ADuC7xxx
类型： MCU
适用于相关产品： ADUC7124
所含物品： 板
ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 66 of 108
COM0DIV2 Register
Name:
MOSI (Master Out, Slave In) Pin
COM0DIV2
Address:
0xFFFF072C
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
Default Value:
0x0000
Access:
Read/write
SCLK (Serial Clock I/O) Pin
COM0DIV2 is a 16-bit fractional baud divide register for
UART0.
COM1DIV2 Register
Name:
COM1DIV2
The master serial clock (SCLK) synchronizes the data being
transmitted and received through the MOSI SCLK period.
Therefore, a byte is transmitted/received after eight SCLK
periods. The SCLK pin is configured as an output in master
mode and as an input in slave mode.
Address:
0xFFFF076C
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
Default Value:
0x0000
Access:
Read/write
)
1
(
2
SPIDIV
f
UCLK
CLOCK
SERIAL
+
×
=
COM1DIV2 is a 16-bit fractional baud divide register for UART1.
The maximum speed of the SPI clock is independent of the
clock divider bits.
Table 99. COMxDIV2 MMR Bit Descriptions
Bit
Name
Description
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10 Mbps.
15
FBEN
Fractional baud rate generator enable bit.
Set by the user to enable the fractional
baud rate generator.
Cleared by the user to generate the baud
rate using the standard 450 UART baud
rate generator.
In both master and slave modes, data is transmitted on one edge
of the SCLK signal and sampled on the other. Therefore, it is
important that the polarity and phase be configured the same
for the master and slave devices.
[14:13]
Reserved.
[12:11]
FBM[1:0]
M if FBM = 0, M = 4 (see The Fractional
Divider section).
CS (SPI Chip Select Input) Pin
[10:0]
FBN[10:0]
N (see The Fractional Divider section).
In SPI slave mode, a transfer is initiated by the assertion of CS,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by deasser-
tion of CS. In slave mode, CS is always an input.
SERIAL PERIPHERAL INTERFACE
The ADuC7124/ADuC7126 integrate a complete hardware serial
peripheral interface (SPI) on chip. SPI is an industry standard,
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and simultaneously received, that is,
full duplex up to a maximum bit rate of 20 Mbps.
In SPI master mode, the CS is an active low output signal. It
asserts itself automatically at the beginning of a transfer and
deasserts itself upon completion.
Configuring External Pins for SPI functionality
The SPI port can be configured for master or slave operation
and typically consists of four pins: MISO, MOSI, SCLK, and CS.
The SPI pins of the ADuC7124/ADuC7126 device are P1.4 to P1.7.
P1.7 is the slave chip select pin. In slave mode, this pin is an
input and must be driven low by the master. In master mode,
this pin is an output and goes low at the beginning of a transfer
and high at the end of a transfer.
MISO (Master In, Slave Out) Pin
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
P1.4 is the SCLK pin.
P1.5 is the master in, slave out (MISO) pin.
P1.6 is the master out, slave in (MOSI) pin.
To configure P1.4 to P1.7 for SPI mode, see the General-
Purpose Input/Output section.
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