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| 型号： | EVAL-ADUC7124QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 60/108页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7124 |
| 设计资源： | EVAL-ADUC7124 Schematic ADUC7124 Eval Brd Gerber Files |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7124 |
| 所含物品： | 板 |
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Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 55 of 108
External Crystal Selection
To switch to an external crystal, the user must follow this
procedure:
1.
Enable the Timer2 interrupt and configure it for a timeout
period of >120 μs.
2.
Follow the write sequence to the PLLCON register, setting
the MDCLK bits to 01 and clearing the OSEL bit.
3.
Force the part into nap mode by following the correct write
sequence to the POWCON0 register.
4.
When the part is interrupted from nap mode by the
Timer2 interrupt source, the clock source has switched to
the external clock.
Example source code:
T2LD = 5;
T2CON = 0x480;
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON0 = 0x27;
// Set core into nap mode
POWKEY2 = 0xF4;
In noisy environments, noise can couple to the external crystal
pins, and PLL may lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is serviced only when the lock is restored.
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA can determine if the reset
came from the watchdog timer.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in
Mode 1. The external clock can be up to 41.78 MHz, providing
the tolerance is 1%.
Example source code:
T2LD = 5;
T2CON = 0x480;
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x03; //Select external clock
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON0 = 0x27;
//
Set core into nap mode
POWKEY2 = 0xF4;
Power Control System
A choice of operating modes is available on the ADuC7124/
ADuC7126. Table 70 describes what part is powered on in the
different modes and indicates the power-up time.
Table 71 gives some typical values of the total current
consumption (analog + digital supply currents) in the different
modes, depending on the clock divider bits. The AC, DAC, I2C,
and SPI are turned off.
Table 70. Operating Modes
Mode
Core
Peripherals
PLL
XTAL/T2/T3
IRQ0 to IRQ3
Start-Up/Power-On Time
Active
On
66 ms at CD = 0
Pause
On
2.6 μs at CD = 0; 247 μs at CD = 7
Nap
On
2.6 μs at CD = 0; 247 μs at CD = 7
Sleep
On
1.58 ms
Stop
On
1.7 ms
Table 71. Typical Current Consumption at 25°C in mA, VDD = 3.3 V
Mode
CD = 0
CD = 1
CD = 2
CD = 3
CD = 4
CD = 5
CD = 6
CD = 7
Active
33.3
23.1
15.4
11.6
9.7
8.8
8.3
8.1
Pause
20.6
12.7
8.8
6.8
5.8
5.3
5.1
4.9
Nap
4.6
Sleep
0.2
Stop
0.2
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