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参数资料
型号： EVAL-ADUC7124QSPZ
厂商： Analog Devices Inc
文件页数： 17/108页
文件大小： 0K
描述： BOARD EVALUATION FOR ADUC7124
设计资源： EVAL-ADUC7124 Schematic
ADUC7124 Eval Brd Gerber Files
标准包装： 1
系列： MicroConverter® ADuC7xxx
类型： MCU
适用于相关产品： ADUC7124
所含物品： 板
ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 16 of 108
Pin No.
Mnemonic
Description
35
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin.
External Interrupt Request 1, Active High (IRQ1).
General-Purpose Input and Output Port 0.5 (P0.5).
ADCBUSY Signal Output (ADCBUSY).
Programmable Logic Array Output Element 2 (PLAO[2]).
36
P2.0/SPM9/PLAO[5]/CONVSTART/SOUT0
General-Purpose Input and Output Port 2.0 (P2.0).
Serial Port Multiplexed (SPM9).
Programmable Logic Array Output Element 5 (PLAO[5]).
Start Conversion Input Signal for ADC (CONVSTART).
UART0 Output (SOUT0).
37
P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0
General-Purpose Input and Output Port 0.7 (P0.7).
Output for External Clock Signal (ECLK).
Input to the Internal Clock Generator Circuits (XCLK).
Serial Port Multiplexed (SPM8).
Programmable Logic Array Output Element 4 (PLAO[4]).
UART0 Input (SIN0).
38
IOGND
Ground for GPIO. Typically connected to DGND.
39
IOVDD
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
40
P3.6/PWMTRIP/PLAI[14]
General-Purpose Input and Output Port 3.6 (P3.6).
PWM Safety Cutoff (PWMTRIP).
Programmable Logic Array Input Element 14 (PLAI[14]).
41
P3.7/PWMSYNC/PLAI[15]
General-Purpose Input and Output Port 3.7 (P3.7).
PWM Synchronization Input/Output (PWMSYNC).
Programmable Logic Array Input Element 15 (PLAI[15]).
42
P1.7/SPM7/DTR/SPICS/PLAO[0]
General-Purpose Input and Output Port 1.7 (P1.7).
Serial Port Multiplexed. UART, SPI (SPM7).
Data Terminal Ready (DTR).
Chip Select (SPICS).
Programmable Logic Array Output Element 0 (PLAO[0]).
43
P1.6/SPM6/PLAI[6]
General-Purpose Input and Output Port 1.6 (P1.6).
Serial Port Multiplexed (SPM6).
Programmable Logic Array Input Element 6 (PLAI[6]).
44
P4.0/PLAO[8]/SIN1
General-Purpose Input and Output Port 4.0 (P4.0).
Programmable Logic Array Output Element 8 (PLAO[8]).
UART1 Input (SIN1).
45
P4.1/PLAO[9]/SOUT1
General-Purpose Input and Output Port 4.1 (P4.1).
Programmable Logic Array Output Element 9 (PLAO[9]).
UART1 Output (SOUT1).
46
P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3
General-Purpose Input and Output Port 1.5 (P1.5).
Serial Port Multiplexed. UART, SPI (SPM5).
Data Carrier Detect (DCD).
Master Input, Slave Output (SPI MISO).
Programmable Logic Array Input Element 5 (PLAI[5]).
External Interrupt Request 3, Active High (IRQ3).
47
P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2
General-Purpose Input and Output Port 1.4 (P1.4).
Serial Port Multiplexed. UART, SPI (SPM4).
Ring Indicator (RI).
Serial Clock Input/Output (SPI SCLK).
Programmable Logic Array Input Element 4 (PLAI[4]).
External Interrupt Request 2, Active High (IRQ2).
48
P1.3/SPM3/CTS/I2C1SDA/PLAI[3]
General-Purpose Input and Output Port 1.3 (P1.3).
Serial Port Multiplexed. UART, I2C1 (SPM3).
Clear to Send (CTS).
I2C1 (I2C1SDA).
Programmable Logic Array Input Element 3 (PLAI[3]).
49
P1.2/SPM2/RTS/I2C1SCL/PLAI[2]
General-Purpose Input and Output Port 1.2 (P1.2).
Serial Port Multiplexed (SPM2).
Ready to Send (RTS).
I2C1 (I2C1SCL).
Programmable Logic Array Input Element 2 (PLAI[2]).
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