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| 型号： | EVAL-ADUC7122QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 84/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7122 |
| 设计资源： | EVAL-ADUC7122 Schematic ADUC7122 Gerber Files ADUC7122 BOM |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7122 |
| 所含物品： | 板 |
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ADuC7122
Rev. 0 | Page 85 of 96
TIMER1—GENERAL-PURPOSE TIMER
Timer1 is a 32-bit general-purpose timer, count down or count
up, with a programmable prescaler. The prescaler source can be
from the 32 kHz internal oscillator, the 32 kHz external crystal,
the core clock, or from the undivided PLL clock output. This
source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a
minimum resolution of 42 ns when operating at CD = 0, the
core is operating at 41.78 MHz, and with a prescaler of 1.
The counter can be formatted as a standard 32-bit value or as
hours:minutes:seconds:hundredths.
Timer1 has a capture register (T1CAP) that can be triggered by
a selected IRQ’s source initial assertion. When triggered, the
current timer value is copied to T1CAP, and the timer keeps
running. This feature can be used to determine the assertion of
an event with increased accuracy.
The Timer1 interface consists of five MMRs, as shown in
Table 150. Timer1 Interface Registers
Register
Description
T1LD
32-bit register. Holds 32-bit unsigned integers.
This register is read only.
T1VAL
32-bit register. Holds 32-bit unsigned integers.
T1CAP
32-bit register. Holds 32-bit unsigned integers.
This register is read only.
T1CLRI
8-bit register. Writing any value to this register clears
the Timer1 interrupt.
T1CON
Configuration MMR.
Note that if the part is in a low power mode, and Timer1 is
clocked from the GPIO or low power oscillator source, then
Timer1 continues to operate.
Timer1 reloads the value from T1LD either when Timer1
overflows or immediately when T1ICLR is written.
Table 151. Timer1 Load Registers
Name
Address
Default Value
Access
T1LD
0xFFFF0320
0x00000
R/W
T1LD is a 32-bit register that holds the 32-bit value that is loaded
into the counter.
Table 152. Timer1 Clear Register
Name
Address
Default Value
Access
T1CLRI
0xFFFF032C
0x00
W
This 8-bit, write-only MMR is written (with any value) by user
code to refresh (reload) Timer1.
Table 153. Timer1 Value Register
Name
Address
Default Value
Access
T1VAL
0xFFFF0324
0x0000
R
T1VAL is a 32-bit register that holds the current value of Timer1.
Table 154. Timer1 Capture Register
Name
Address
Default Value
Access
T1CAP
0xFFFF0330
0x00
R
This is a 32-bit register that holds the 32-bit value captured by
an enabled IRQ event.
Table 155. Timer1 Control Register.
Name
Address
Default Value
Access
T1CON
0xFFFF0328
0x0000
R/W
This 32-bit MMR configures the mode of operation of Timer1.
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