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| 型号： | EVAL-ADUC7122QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7122 |
| 设计资源： | EVAL-ADUC7122 Schematic ADUC7122 Gerber Files ADUC7122 BOM |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7122 |
| 所含物品： | 板 |
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ADuC7122
Rev. 0 | Page 35 of 96
POWER SUPPLY MONITOR
The power supply monitor on the ADuC7122 indicates when
the IOVDD supply pin drops below one of two supply trip points.
The monitor function is controlled via the PSMCON register.
If enabled in the IRQEN or FIQEN register, the monitor inter-
rupts the core using the PSMI bit in the PSMCON MMR. This
bit is cleared immediately when CMP goes high. Note that if
the interrupt generated is exited before CMP goes high (IOVDD
is above the trip point), no further interrupts are generated
until CMP returns high. The user should ensure that code
execution remains within the ISR until CMP returns high.
This monitor function allows the user to save working registers
to avoid possible data loss due to the low supply or brownout
conditions. It also ensures that normal code execution does not
resume until a safe supply level has been established.
When the ADC channel selection bits are configured to
IOVDD_MON (ADCCP[4:0] = 10011), this permits the ADC
to convert the voltage available at the input of the power supply
monitor comparator. When measuring an internal channel, the
internal buffer must be enabled. The internal buffer should be
enabled to isolate from external interference when sampling any
of the internal channels. Before measuring this voltage, the
following sequence is required:
1.
Measure VREF using the ADC.
2.
Set ADCCP = IOVDD_MON channel.
3.
Set a typical delay of 60 μs.
4.
Perform ADC conversion on the IOVDD_MON channel
(use an ADCCON value of 0x2AA3 for optimum results).
The delay between the ADC mux select switching and the
initiation of the conversion is required to allow the voltage on
the ADC sampling capacitor to settle to the divided down
supply voltage.
Table 36. REFCON MMR Bit Designations (Address = 0xFFFF0480, Default Value = 0x01)
Bit
Description
7:1
Reserved.
2
Reserved. Always set to 1. This bit outputs the buffered version of the internal 2.5 V reference onto BUF_VREF1 and BUF_VREF2. To
disable this buffer, the user must disable the internal reference by clearing REFCON = 0x00.
1
Internal 2.5 V reference output enable.
Set by the user to connect the internal 2.5 V reference to the VREF_2.5 pin.
Cleared by the user to disconnect the reference from the VREF_2.5 pin. This pin should also be cleared to connect an external
reference source to the VREF_2.5 pin.
0
Internal 1.2 V reference output enable.
Set by the user to connect the internal 1.2 V reference to the VREF_1.2 pin.
Cleared by the user to disconnect the reference from the VREF_1.2 pin.
Table 37. PSMCON MMR Bit Designations (Address = 0xFFFF0440, Default Value = 0x08 or 0x00 (Dependent on Device Supply Level)
Bit
Name
Description
7:4
Reserved
Reserved bits. Clear to 0.
3
CMP
Comparator bit. This is a read-only bit that directly reflects the state of the comparator.
Read 1 indicates the IOVDD supply is above its selected trip point or the PSM is in power-down mode.
Read 0 indicates the IOVDD supply is below its selected trip point. This bit should be set before leaving the interrupt
service routine.
2
TP
Trip point selection bit.
0 = 2.79 V
1 = 3.07 V
1
PSMEN
Power supply monitor enable bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
0
PSMI
Power supply monitor interrupt bit. This bit is set high by the ADuC7122 if CMP is low, indicating low I/O supply. The
PSMI bit can be used to interrupt the processor. When CMP returns high, the PSMI bit can be cleared by writing a 1 to
this location. A write of 0 has no effect. There is no timeout delay. PSMI can be cleared immediately when CMP goes
high.
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