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| 型号： | EVAL-ADUC7122QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 83/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7122 |
| 设计资源： | EVAL-ADUC7122 Schematic ADUC7122 Gerber Files ADUC7122 BOM |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7122 |
| 所含物品： | 板 |
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ADuC7122
Rev. 0 | Page 84 of 96
The Timer0 interface consists of six MMRs, shown in Table 143.
Table 143. Timer0 Interface MMRs
Name
Description
T0LD
16-bit register that holds the 16-bit value
loaded into the counter. Available only in
16-bit mode.
T0CAP
16-bit register that holds the 16-bit value
captured by an enabled IRQ event. Available
only in 16-bit mode.
T0VAL0/T0VAL1
TOVAL0 is a 16-bit register that holds the 16
least significant bits (LSBs).
T0VAL1 is a 32-bit register that holds the 32
most significant bits (MSBs).
T0CLRI
8-bit register. Writing any value to this register
clears the interrupt. Available only in 16-bit
mode.
T0CON
Configuration MMR.
Table 144. Timer0 Value Register
Name
Address
Default Value
Access
T0VAL0
0xFFFF0304
0x00,
R
T0VAL1
0xFFFF0308
0x00
R
T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold
the 16 least significant bits and 32 most significant bits,
respectively. T0VAL0 and T0VAL1 are read-only. In 16-bit
mode, 16-bit T0VAL0 is used. In 48-bit mode, both 16-bit
T0VAL0 and 32-bit T0VAL1 are used.
Table 145. Timer0 Capture Register
Name
Address
Default Value
Access
T0CAP
0xFFFF0314
0x00
R
This is a 16-bit register that holds the 16-bit value captured by
an enabled IRQ event; it is only available in 16-bit mode.
Table 146. Timer0 Control Register
Name
Address
Default Value
Access
T0CON
0xFFFF030C
0x00
R/W
The 17-bit MMR configures the mode of operation of Timer0.
Table 147. T0CON MMR Bit Designations
Bit
Value
Description
31:18
Reserved.
17
Event select bit.
Set by the user to enable time capture of an
event.
Cleared by the user to disable time capture of
an event.
16:12
Event select (ES) range, 0 to 17. The events are
as described in the Timers section.
11
Reserved.
10:9
Clock select.
00
Internal 32 kHz oscillator.
01
UCLK.
10
External 32 kHz crystal.
11
HCLK.
8
Count up. Available only in 16-bit mode.
Set by the user for Timer0 to count up.
Cleared by the user for Timer0 to count down
(default).
7
Timer0 enable bit.
Set by the user to enable Timer0.
Cleared by the user to disable Timer0
(default).
6
Timer0 mode.
Set by the user to operate in periodic mode.
Cleared by the user to operate in free-running
mode (default).
5
Reserved.
4
Timer0 mode of operation.
0
16-bit operation (default).
1
48-bit operation.
3:0
Prescaler.
0000
Source clock/1 (default).
0100
Source clock/16.
1000
Source clock/256.
1111
Source clock/32,768.
Table 148. Timer0 Load Registers
Name
Address
Default Value
Access
T0LD
0xFFFF0300
0x00
R/W
T0LD is a 16-bit register that holds the 16-bit value that is
loaded into the counter; it is available only in 16-bit mode.
Table 149. Timer0 Clear Register
Name
Address
Default Value
Access
T0CLRI
0xFFFF0310
0x00
W
This 8-bit, write-only MMR is written (with any value) by user
code to refresh (reload) Timer0.
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