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| 型号： | EVAL-ADUC7122QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 62/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7122 |
| 设计资源： | EVAL-ADUC7122 Schematic ADUC7122 Gerber Files ADUC7122 BOM |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7122 |
| 所含物品： | 板 |
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ADuC7122
Rev. 0 | Page 65 of 96
Bit
Name
Description
2
I2CGCEN
I2C general call enable.
Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then
recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hardware) as
the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This command can be used to
reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the
data byte, the general call interrupt status bit sets on any general call.
The user must take corrective action by reprogramming the device address.
Set this bit to allow the slave ACK I2C general call commands.
Clear to disable recognition of general call commands.
1
ADR10EN
I2C 10-bit address mode.
Set to 1 to enable 10-bit address mode.
Clear to 0 to enable normal address mode.
0
I2CSEN
I2C slave enable bit.
Set by the user to enable I2C slave mode.
Clear to disable I2C slave mode.
I2C Slave Status Registers
Name:
I2C0SSTA, I2C1SSTA
Address:
0xFFFF08AC, 0xFFFF092C
Default Value:
0x0000, 0x0000
Access:
Read only
Function:
This 16-bit MMR is the I2C status register in slave mode.
Table 109. I2CxSSTA MMR Bit Designations
Bit
Name
Description
15
Reserved bit.
14
I2CSTA
This bit is set to 1 if a start condition followed by a matching address is detected. It is also set if a start byte (0x01) is
received, or if general calls are enabled and a general call code of 0x00 is received.
This bit is cleared upon receiving a stop condition.
13
I2CREPS
This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition.
12-11
I2CID[1:0]
I2C address matching register. These bits indicate which I2CxIDx register matches the received address.
00 = received address matches I2CxID0.
01 = received address matches I2CxID1.
10 = received address matches I2CxID2.
11 = received address matches I2CxID3.
10
I2CSS
I2C stop condition after start detected bit.
This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the
I2CSSENI bit in I2CxSCTL is set, an interrupt is generated.
This bit is cleared by reading this register.
9:8
I2CGCID[1:0]
I2C general call ID bits.
00 = no general call received.
01 = general call reset and program address.
10 = general program address.
11 = general call matching alternative ID.
Note that these bits are not cleared by a general call reset command.
Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCTL.
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