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| 型号： | EVAL-ADUC7122QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 80/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7122 |
| 设计资源： | EVAL-ADUC7122 Schematic ADUC7122 Gerber Files ADUC7122 BOM |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7122 |
| 所含物品： | 板 |
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ADuC7122
Rev. 0 | Page 81 of 96
IRQSTAN Register
If IRQCONN[0] is asserted and IRQVEC is read, then one of
these bits is asserted. The bit that asserts depends on the prior-
ity of the IRQ. For example, if the IRQ is of Priority 0 then Bit 0
asserts; if it is Priority 1, then Bit 1 asserts. When a bit is set in
this register, all interrupts of that priority and lower are blocked.
To clear a bit in this register, all bits of a higher priority must
be cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
Name:
IRQSTAN
Address:
0xFFFF003C
Default Value:
0x00000000
Access:
Read and write
Table 137. IRQSTAN MMR Bit Designations
Bit
Name
Description
31:8
Reserved
These bits are reserved and should not be
written to.
7:0
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
FIQVEC Register
The FIQ interrupt vector register, FIQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should only be read when
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
Name:
FIQVEC
Address:
0xFFFF011C
Default Value:
0x00000000
Access:
Read only
Table 138. FIQVEC MMR Bit Designations
Bit
Type
Initial
Value
Description
31:23
Read only
0
Always read as 0.
22:7
R/W
0
IRQBASE register value.
6:2
0
Highest priority FIQ source. This is
a value between 0 to 27, which
represents the possible interrupt
sources. For example, if the
highest currently active FIQ is
Timer1, then these bits are 00011.
1:0
Reserved
0
Reserved bits.
FIQSTAN Register
If IRQCONN[1] is asserted and FIQVEC is read then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. For example, if the FIQ is of Priority 0, then Bit 0
asserts; if it is Priority 1, then Bit 1 asserts.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit as a time. For
example, if this register is set to 0x09, then writing 0xFF
changes the register to 0x08 and writing 0xFF a second time
changes the register to 0x00.
Name:
FIQSTAN
Address:
0xFFFF013C
Default Value:
0x00000000
Access:
Read and write
Table 139. FIQSTAN MMR Bit Designations
Bit
Name
Description
31:8
Reserved
These bits are reserved and should not be
written to.
7:0
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
External Interrupts (IRQ0 to IRQ5)
The ADuC7122 provides up to six external interrupt sources.
These external interrupts can be individually configured as level
or rising/falling edge triggered.
To enable the external interrupt source, the appropriate bit must
first be set in the FIQEN or IRQEN register. To select the
required edge or level to trigger on, the IRQCONE register
must be appropriately configured.
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in the IRQCLRE register.
IRQCONE Register
Name:
IRQCONE
Address:
0xFFFF0034
Default Value:
0x00000000
Access:
Read and write
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