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| 型号： | EVAL-ADUC7122QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 79/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7122 |
| 设计资源： | EVAL-ADUC7122 Schematic ADUC7122 Gerber Files ADUC7122 BOM |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7122 |
| 所含物品： | 板 |
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ADuC7122
Rev. 0 | Page 80 of 96
Table 133. IRQP1 MMR Bit Designations
Bit
Name
Description
31
Reserved
Reserved bit.
30:28
I2C0MPI
A priority level of 0 to 7 can be set for the
I2C0 master.
27
Reserved
Reserved bit.
26:24
SPIPI
A priority level of 0 to 7 can be set for the
SPI.
23
Reserved
Reserved bit.
22:20
UARTPI
A priority level of 0 to 7 can be set for the
UART.
19
Reserved
Reserved bit.
18:16
ADCPI
A priority level of 0 to 7 can be set for the
ADC interrupt source.
15
Reserved
Reserved bit.
14:12
Flash1PI
A priority level of 0 to 7 can be set for the
Flash Block 1 controller interrupt source.
11
Reserved
Reserved bit.
10:8
Flash0PI
A priority level of 0 to 7 can be set for the
Flash Block 0 controller interrupt source.
7:3
Reserved
Reserved bits.
2:0
PSMPI
A priority level of 0 to 7 can be set for the
Power supply monitor interrupt source.
IRQP2 Register
Name:
IRQP2
Address:
0xFFFF0028
Default Value:
0x00000000
Access:
Read and write
Table 134. IRQP2 MMR Bit Designations
Bit
Name
Description
31
Reserved
Reserved bit.
30:28
PWMPI
A priority level of 0 to 7 can be set for PWM.
27
Reserved
Reserved bit.
26:24
IRQ3PI
A priority level of 0 to 7 can be set for IRQ3.
23
Reserved
Reserved bit.
22:20
IRQ2PI
A priority level of 0 to 7 can be set for IRQ2.
19
Reserved
Reserved bit.
18:16
IRQ1PI
A priority level of 0 to 7 can be set for IRQ1.
15
Reserved
Reserved bit.
14:12
IRQ0PI
A priority level of 0 to 7 can be set for IRQ0.
11
Reserved
Reserved bit.
10:8
I2C1SPI
A priority level of 0 to 7 can be set for I2C1
slave.
7
Reserved
Reserved bit.
6:4
I2C1MPI
A priority level of 0 to 7 can be set for I2C1
master.
3
Reserved
Reserved bit.
2:0
I2C0SPI
A priority level of 0 to 7 can be set for I2C0
slave.
IRQP3 Register
Name:
IRQP3
Address:
0xFFFF002C
Default Value:
0x00000000
Access:
Read and write
Table 135. IRQP3 MMR Bit Designations
Bit
Name
Description
31:15
Reserved
Reserved bit.
14:12
PLA1PI
A priority level of 0 to 7 can be set for PLA0.
11
Reserved
Reserved bit.
10:8
PLA0PI
A priority level of 0 to 7 can be set for PLA0.
7
Reserved
Reserved bit.
6:4
IRQ5PI
A priority level of 0 to 7 can be set for IRQ5.
3
Reserved
Reserved bit.
2:0
IRQ4PI
A priority level of 0 to 7 can be set for IRQ4.
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits. The first enables nesting and prioritization
of IRQ interrupts and the other enables nesting and prioritiza-
tion of FIQ interrupts.
If these bits are cleared, then FIQs and IRQs can still be used,
but it is not possible to nest IRQs or FIQs. Neither is it possible
to set an interrupt source priority level. In this default state, an
FIQ does have a higher priority than an IRQ.
Name:
IRQCONN
Address:
0xFFFF0030
Default Value:
0x00000000
Access:
Read and write
Table 136. IRQCONN MMR Bit Designations
Bit
Name
Description
31:2
Reserved
These bits are reserved and should not be
written to.
1
ENFIQN
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
0
ENIRQN
Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no nesting
or prioritization of IRQs is allowed.
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