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| 型号： | EVAL-ADUC7122QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 66/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7122 |
| 设计资源： | EVAL-ADUC7122 Schematic ADUC7122 Gerber Files ADUC7122 BOM |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7122 |
| 所含物品： | 板 |
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ADuC7122
Rev. 0 | Page 69 of 96
SERIAL PERIPHERAL INTERFACE
The ADuC7122 integrates a complete hardware serial peri-
pheral interface (SPI) on chip. SPI is an industry standard,
synchronous serial interface that allows eight bits of data to
be synchronously transmitted and simultaneously received,
that is, full duplex up to a maximum bit rate of 20 Mb.
The SPI port can be configured for master or slave operation
and typically consists of four pins: SPIMISO, SPIMOSI,
SPICLK, and SPICS.
SPIMISO (MASTER IN, SLAVE OUT) PIN
The SPIMISO pin is configured as an input line in master mode
and an output line in slave mode. The SPIMISO line on the
master (data in) should be connected to the SPIMISO line in
the slave device (data out). The data is transferred as byte wide
(8-bit) serial data, MSB first.
SPIMOSI (MASTER OUT, SLAVE IN) PIN
The SPIMOSI pin is configured as an output line in master
mode and an input line in slave mode. The SPIMOSI line on the
master (data out) should be connected to the SPIMOSI line in
the slave device (data in). The data is transferred as byte wide
(8-bit) serial data, MSB first.
SPICLK (SERIAL CLOCK I/O) PIN
The master serial clock (SPICLK) synchronizes the data being
transmitted and received through the MOSI SPICLK period.
Therefore, a byte is transmitted/received after eight SPICLK
periods. The SPICLK pin is configured as an output in master
mode and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
)
1
(
2
SPIDIV
f
UCLK
CLOCK
SERIAL
The maximum speed of the SPI clock is independent on the
clock divider bits.
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10 Mb.
In both master and slave modes, data is transmitted on one edge
of the SPICLK signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
SPI CHIP SELECT (SPICS INPUT) PIN
In SPI slave mode, a transfer is initiated by the assertion of
SPICS, which is an active low input signal. The SPI port then
transmits and receives 8-bit data until the transfer is concluded
by deassertion of SPICS. In slave mode, SPICS is always an input.
In SPI master mode, SPICS is an active low output signal. It
asserts itself automatically at the beginning of a transfer and
deasserts itself upon completion.
CONFIGURING EXTERNAL PINS FOR SPI
FUNCTIONALITY
The SPI pins of the ADuC7122 device are P0.2 to P0.5.
P0.5 is the slave chip select pin. In slave mode, this pin is an
input and must be driven low by the master. In master mode,
this pin is an output and goes low at the beginning of a transfer
and high at the end of a transfer.
P0.2 is the SPICLK pin.
P0.3 is the master in, slave out (SPIMISO) pin.
P0.4 is the master out, slave in (SPIMOSI) pin.
To configure P0.2 to P0.5 for SPI mode, see the General-
Purpose I/O section.
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