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| 型号： | EVAL-ADUC7122QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 61/96页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7122 |
| 设计资源： | EVAL-ADUC7122 Schematic ADUC7122 Gerber Files ADUC7122 BOM |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7122 |
| 所含物品： | 板 |
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ADuC7122
Rev. 0 | Page 64 of 96
I2C Slave Registers
I2C Slave Control Register
Name:
I2C0SCTL, I2C1SCTL
Address:
0xFFFF08A8, 0xFFFF0928
Default Value:
0x0000, 0x000
Access:
Read/write
Function:
This 16-bit MMR configures the I2C peripheral in slave mode.
Table 108. I2CxSCTL MMR Bit Designations
Bit
Name
Description
15:11
Reserved bits.
10
I2CSTXENI
Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
9
I2CSRXENI
Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
8
I2CSSENI
I2C stop condition detected interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I2C bus.
Clear this interrupt source.
7
I2CNACKEN
I2C NACK enable bit.
Set this bit to NACK the next byte in the transmission sequence.
Clear this bit to let the hardware control the ACK/NACK sequence.
6
I2CSSEN
I2C slave SCLx stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCLx is low, setting this bit forces the device to hold SCLx low until
I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCLx low after the next falling edge.
Clear this bit to disable clock stretching.
5
I2CSETEN
I2C early transmit interrupt enable bit.
Setting this bit enables a transmit request interrupt just after the positive edge of SCLx during the read bit
transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCLx during the read bit
transmission.
4
I2CGCCLR
I2C general call status and ID clear bit.
Writing a 1 to this bit clears the general call status (I2CGC) and ID (I2CGCID[1:0]) bits in the I2CxSSTA register.
Clear this bit at all other times.
3
I2CHGCEN
I2C hardware general call enable.
Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a
data byte, the device checks the contents of I2CxALT against the receive register. If the contents match, the device
has received a hardware general call. This method is used if a device needs urgent attention from a master device
without knowing which master it needs to turn to. This is a broadcast message to all master devices on the bus. The
ADuC7122 watches for these addresses. The device that requires attention embeds its own address into the
message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately.
The LSB of the I2CxALT register should always be written to 1, as per the I2C January 2000 bus specification.
Set this bit and I2CGCEN to enable hardware general call recognition in slave mode.
Clear this bit to disable recognition of hardware general call commands.
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