- 您现在的位置：买卖IC网 > Datasheet目录369 > W947D2HBJX5E (Winbond Electronics)IC LPDDR SDRAM 128MBIT 90VFBGA Datasheet资料下载
参数资料
| 型号： | W947D2HBJX5E |
| 厂商： | Winbond Electronics |
| 文件页数： | 54/60页 |
| 文件大小： | 0K |
| 描述： | IC LPDDR SDRAM 128MBIT 90VFBGA |
| 标准包装： | 240 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR SDRAM |
| 存储容量： | 128M（4Mx32） |
| 速度： | 200MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 90-TFBGA |
| 供应商设备封装： | 90-VFBGA（8x13） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页当前第54页第55页第56页第57页第58页第59页第60页
W947D6HB / W947D2HB
128Mb Mobile LPDDR
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters
are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins
driving (LZ).
20. tDQSQ consists of data pin skew and output pattern effects,
and p-channel to n-channel variation of the
output drivers for any given cycle.
21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before
the corresponding CK edge. A valid transition is defined as monotonic and meeting the input slew rate
specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning
from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-
down element in the system. It is recommended to turn off the weak pull-down element during read and write
bursts (DQS drivers enabled).
24. At least one clock cycle is required during tWR time when in auto precharge mode.
25. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms, if not already an integer,
round to the next higher
integer.
26. There must be at least two clock pulses during the tXSR period.
27. There must be at least one clock pulse during the tXP period.
28. A maximum of 8 Refresh commands can be posted to any given LPDDR SDRAM, meaning that the maximum
absolute interval between any Refresh command and the next Refresh command is 8*tREFI.
8.5.1 CAS Latency Definition (With CL=3)
T0
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CK
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
DQS
CL=3
t DQSCKmin
t RPRE
t DQSCKmin
t RPST
All DQ,
collectively
t LZmin
t LZmin
T2
T2n
T3
T3n
T4
T4n
T5
T5n
1)DQ transitioning after DQS transition define tDQSQ window.
2)ALL DQ must transition by tDQSQ after DQS transitions, regardless of tAC
3)tAC is the DQ output window relative to CK,and is the long term component of DQ skew.
Publication Release Date:Jun,17, 2011
- 54 -
Revision A01-003
相关PDF资料 |
PDF描述 |
|---|---|
| W948D2FBJX5E | IC LPDDR SDRAM 256MBIT 90VFBGA |
| W949D2CBJX5E | IC LPDDR SDRAM 512MBIT 90VFBGA |
| W971GG6JB25I | IC DDR2 SDRAM 1GBIT 84WBGA |
| W971GG8JB-25 | IC DDR2 SDRAM 1GBIT 60WBGA |
| W9725G6IB-25 | IC DDR2-800 SDRAM 256MB 84-WBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W947D2HBJX5I | 制造商:WINBOND 制造商全称:Winbond 功能描述:128Mb Mobile LPDDR |
| W947D2HBJX6E | 制造商:Winbond Electronics Corp 功能描述:IC LPDDR SDRAM 128MBIT 90VFBGA |
| W947D2HBJX6G | 制造商:WINBOND 制造商全称:Winbond 功能描述:128Mb Mobile LPDDR |
| W947D6HB | 制造商:WINBOND 制造商全称:Winbond 功能描述:128Mb Mobile LPDDR |
| W947D6HBHX5E | 功能描述:IC LPDDR SDRAM 128MBIT 60VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:4G（256M x 16） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP I 包装:Digi-Reel® 其它名称:557-1461-6 |
发布紧急采购，3分钟左右您将得到回复。