- 您现在的位置：买卖IC网 > PDF目录17109 > EVAL-ADUC7023QSPZ (Analog Devices Inc)KIT DEV FOR ADUC7023 QUICK START PDF资料下载
参数资料
| 型号： | EVAL-ADUC7023QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 81/96页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC7023 QUICK START |
| 标准包装： | 1 |
| 类型： | MCU |
| 适用于相关产品： | ARM7TDMI |
| 所含物品： | 板 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页当前第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页
ADuC7023
Data Sheet
| Page 82 of 96
FIQSTAN Register
If IRQCONN Bit 1 is asserted and FIQVEC is read, then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0, then Bit 0 asserts. If the FIQ
is of Priority 1, then Bit 1 asserts, and so forth.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, then writing 0xFF changes
the register to 0x08 and writing 0xFF a second time changes the
register to 0x00.
Name:
FIQSTAN
Address:
0xFFFF013C
Default value: 0x00000000
Access:
Read/write
Table 98. FIQSTAN MMR Bit Designations
Bit
Name
Description
31 to 8
Reserved
These bits are reserved and should not be
written to.
7 to 0
This bit is set to 1 to enables nesting of
FIQ interrupts.
When this bit is cleared, it means no
nesting or prioritization of FIQs is
allowed.
External Interrupts and PLA interrupts
The ADuC7023 provides up to four external interrupt sources
and two PLA interrupt sources. These external interrupts can be
individually configured as level or rising/falling edge triggered.
To enable the external interrupt source or the PLA interrupt
source, the appropriate bit must be set in the FIQEN or IRQEN
register. To select the required edge or level to trigger on, the
IRQCONE register must be appropriately configured.
To properly clear an edge-based external IRQ interrupt or an edge-
based PLA interrupt, set the appropriate bit in the IRQCLRE
register.
IRQCONE Register
Name:
IRQCONE
Address:
0xFFFF0034
Default value: 0x00000000
Access:
Read and write
Table 99. IRQCONE MMR Bit Designations
Bit
Value
Name
Description
31 to 12
Reserved
These bits are reserved and
should not be written to.
11 to 10
11
PLA1SRC[1:0]
PLA IRQ1 triggers on falling
edge.
10
PLA IRQ1 triggers on rising
edge.
01
PLA IRQ1 triggers on low
level.
00
PLA IRQ1 triggers on high
level.
9 to 8
11
IRQ3SRC[1:0]
External IRQ3 triggers on
falling edge.
10
External IRQ3 triggers on
rising edge.
01
External IRQ3 triggers on
low level.
00
External IRQ3 triggers on
high level.
7 to 6
11
IRQ2SRC[1:0]
External IRQ2 triggers on
falling edge.
10
External IRQ2 triggers on
rising edge.
01
External IRQ2 triggers on
low level.
00
External IRQ2 triggers on
high level.
5 to 4
11
PLA0SRC[1:0]
PLA IRQ0 triggers on falling
edge.
10
PLA IRQ0 triggers on rising
edge.
01
PLA IRQ0 triggers on low
level.
00
PLA IRQ0 triggers on high
level.
3 to 2
11
IRQ1SRC[1:0]
External IRQ1 triggers on
falling edge.
10
External IRQ1 triggers on
rising edge.
01
External IRQ1 triggers on
low level.
00
External IRQ1 triggers on
high level.
1 to 0
11
IRQ0SRC[1:0]
External IRQ0 triggers on
falling edge.
10
External IRQ0 triggers on
rising edge.
01
External IRQ0 triggers on
low level.
00
External IRQ0 triggers on
high level.
Rev. E
相关PDF资料 |
PDF描述 |
|---|---|
| RPS-1K-6-250/2.0-9 | HEAT SHRINK SLEEVE |
| ECM30DCWH | CONN EDGECARD 60POS DIP .156 SLD |
| SC43B-3R3 | INDUCTOR SMD 3.3UH 1.44A 7.96MHZ |
| EVAL-ADUC842QSPZ | KIT DEV QUICK START ADUC842 |
| EVAL-ADUC841QSPZ | KIT DEV QUICK START ADUC841 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-ADUC7023QSPZ1 | 功能描述:BOARD EVAL FOR ADUC7023 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| EVAL-ADuC7023QSPZ2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler |
| EVALADUC7023QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVAL-ADUC7024QS | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk |
| EVAL-ADUC7024QS-U2 | 制造商:Analog Devices 功能描述:QUICK START DEVL SYST EVAL BOARD I.C. - Bulk |
发布紧急采购，3分钟左右您将得到回复。