- 您现在的位置：买卖IC网 > PDF目录17109 > EVAL-ADUC7023QSPZ (Analog Devices Inc)KIT DEV FOR ADUC7023 QUICK START PDF资料下载
参数资料
| 型号： | EVAL-ADUC7023QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 80/96页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC7023 QUICK START |
| 标准包装： | 1 |
| 类型： | MCU |
| 适用于相关产品： | ARM7TDMI |
| 所含物品： | 板 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页当前第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页
Data Sheet
ADuC7023
| Page 81 of 96
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register.
It contains two active bits. The first to enable nesting and
prioritization of IRQ interrupts and the other to enable
nesting and prioritization of FIQ interrupts.
If these bits are cleared, then FIQs and IRQs may still be used,
but it is not possible to nest IRQs or FIQs. Neither is it possible
to set an interrupt source priority level. In this default state, an
FIQ does have a higher priority than an IRQ.
Name:
IRQCONN
Address:
0xFFFF0030
Default value: 0x00000000
Access:
Read and write
Table 95. IRQCONN MMR Bit Designations
Bit
Name
Description
31 to 2
Reserved
These bits are reserved and should not be
written to.
1
ENFIQN
This bit is set to 1 to enable nesting of FIQ
interrupts.
This bit is cleared to mean no nesting or
prioritization of FIQs is allowed.
0
ENIRQN
This bit is set to 1 to enable nesting of IRQ
interrupts.
When this bit is cleared, it means no
nesting or prioritization of IRQs is
allowed.
IRQSTAN Register
If IRQCONN Bit 0 is asserted and IRQVEC is read then one of
these bits is asserted. The bit that asserts depends on the priority of
the IRQ. If the IRQ is of Priority 0, then Bit 0 asserts. If the IRQ is
of Priority 1, then Bit 1 asserts, and so forth. When a bit is set in
this register, all interrupts of that priority and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
Name:
IRQSTAN
Address:
0xFFFF003C
Default value: 0x00000000
Access:
Read and write
Table 96. IRQSTAN MMR Bit Designations
Bit
Name
Description
31 to 8
Reserved
These bits are reserved and should not be
written to.
7 to 0
This bit is set to 1 to enable nesting of FIQ
interrupts.
When this bit is cleared, it means no
nesting or prioritization of FIQs is
allowed.
FIQVEC Register
The FIQ interrupt vector register, FIQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should only be read when
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
Name:
FIQVEC
Address:
0xFFFF011C
Default value: 0x00000000
Access:
Read only
Table 97. FIQVEC MMR Bit Designations
Bit
Type
Initial
Value
Description
31 to 23
Read only
0
Always read as 0.
22 to 7
R/W
0
IRQBASE register value.
6 to 2
0
Highest priority source. This
is a value between 0 and 27
that represents the possible
interrupt sources. For
example, if the highest
currently active FIQ is
Timer 2, then these bits are
[00100].
1 to 0
Reserved
0
Reserved bits.
Rev. E
相关PDF资料 |
PDF描述 |
|---|---|
| RPS-1K-6-250/2.0-9 | HEAT SHRINK SLEEVE |
| ECM30DCWH | CONN EDGECARD 60POS DIP .156 SLD |
| SC43B-3R3 | INDUCTOR SMD 3.3UH 1.44A 7.96MHZ |
| EVAL-ADUC842QSPZ | KIT DEV QUICK START ADUC842 |
| EVAL-ADUC841QSPZ | KIT DEV QUICK START ADUC841 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-ADUC7023QSPZ1 | 功能描述:BOARD EVAL FOR ADUC7023 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| EVAL-ADuC7023QSPZ2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler |
| EVALADUC7023QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVAL-ADUC7024QS | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk |
| EVAL-ADUC7024QS-U2 | 制造商:Analog Devices 功能描述:QUICK START DEVL SYST EVAL BOARD I.C. - Bulk |
发布紧急采购，3分钟左右您将得到回复。