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参数资料
型号： EVAL-ADUC7023QSPZ
厂商： Analog Devices Inc
文件页数： 19/96页
文件大小： 0K
描述： KIT DEV FOR ADUC7023 QUICK START
标准包装： 1
类型： MCU
适用于相关产品： ARM7TDMI
所含物品： 板
ADuC7023
Data Sheet
| Page 26 of 96
Address
Name
Byte
Access Type
Default Value
Description
0x0530
ADCGN
2
R/W
Factory configured
ADC gain calibration MMR.
0x0534
ADCOF
2
R/W
Factory configured
ADC offset calibration MMR.
0x0544
TSCON
1
R/W
0x00
Temperature sensor chopping enable register.
0x0548
TEMPREF
2
R/W
Factory configured
Temperature sensor reference value.
Table 16. DAC Address Base = 0xFFFF0600
Address
Name
Byte
Access Type
Default Value
Description
0x0600
DAC0CON
1
R/W
0x00
DAC0 control MMR.
0x0604
DAC0DAT
4
R/W
0x00000000
DAC0 data MMR.
0x0608
DAC1CON
1
R/W
0x00
DAC1 control MMR.
0x060C
DAC1DAT
4
R/W
0x00000000
DAC1 data MMR.
0x0610
DAC2CON
1
R/W
0x00
DAC2 control MMR.
0x0614
DAC2DAT
4
R/W
0x00000000
DAC2 data MMR.
0x0618
DAC3CON
1
R/W
0x00
DAC3 control MMR.
0x061C
DAC3DAT
4
R/W
0x00000000
DAC3 data MMR.
0x0654
DACBCFG
1
R/W
0x00
DAC Configuration MMR
0x0650
DACBKEY0
2
W
0x0000
DAC Key0 MMR
0x0658
DACBKEY1
2
W
0x0000
DAC Key1 MMR
Table 17. I2C0 Base Address = 0XFFFF0800
Address
Name
Byte
Access Type
Default Value
Description
0x0800
I2C0MCON
2
R/W
0x0000
I2C0 master control register.
0x0804
I2C0MSTA
2
R
0x0000
I2C0 master status register.
0x0808
I2C0MRX
1
R
0x00
I2C0 master receive register.
0x080C
I2C0MTX
1
W
0x00
I2C0 master transmit register.
0x0810
I2C0MCNT0
2
R/W
0x0000
I2C0 master read count register. Write the number of required
bytes into this register prior to reading from a slave device.
0x0814
I2C0MCNT1
1
R
0x00
I2C0 master current read count register. This register contains the
number of bytes already received during a read from slave sequence.
0x0818
I2C0ADR0
1
R/W
0x00
I2C0 address byte register. Write the required slave address in here
prior to communications.
0x081C
I2C0ADR1
1
R/W
0x00
I2C0 address byte register. Write the required slave address in here
prior to communications. Used in 10-bit mode only.
0x0824
I2C0DIV
2
R/W
0x1F1F
I2C0 clock control register. Used to configure the SCL frequency.
0x0828
I2C0SCON
2
R/W
0x0000
I2C0 slave control register.
0x082C
I2C0SSTA
2
R/W
0x0000
I2C0 slave status register.
0x0830
I2C0SRX
1
R
0x00
I2C0 slave receive register.
0x0834
I2C0STX
1
W
0x00
I2C0 slave transmit register.
0x0838
I2C0ALT
1
R/W
0x00
I2C0 hardware general call recognition register.
0x083C
I2C0ID0
1
R/W
0x00
I2C0 slave ID0 register. Slave bus ID register.
0x0840
I2C0ID1
1
R/W
0x00
I2C0 slave ID1 register. Slave bus ID register.
0x0844
I2C0ID2
1
R/W
0x00
I2C0 slave ID2 register. Slave bus ID register.
0x0848
I2C0ID3
1
R/W
0x00
I2C0 slave ID3 register. Slave bus ID register.
0x084C
I2C0FSTA
2
R/W
0x0000
I2C0 FIFO status register. Used in both master and slave modes.
Table 18. I2C1 Base Address = 0XFFFF0900
Address
Name
Byte
Access Type
Default Value
Description
0x0900
I2C1MCON
2
R/W
0x0000
I2C1 master control register.
0x0904
I2C1MSTA
2
R
0x0000
I2C1 master status register.
0x0908
I2C1MRX
1
R
0x00
I2C1 master receive register.
0x090C
I2C1MTX
1
W
0x00
I2C1 master transmit register.
0x0910
I2C1MCNT0
2
R/W
0x0000
I2C1 master read count register. Write the number of required bytes
into this register prior to reading from a slave device.
Rev. E
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