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| 型号： | EVAL-ADUC7023QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 47/96页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC7023 QUICK START |
| 标准包装： | 1 |
| 类型： | MCU |
| 适用于相关产品： | ARM7TDMI |
| 所含物品： | 板 |
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Data Sheet
ADuC7023
| Page 51 of 96
DIGITAL PERIPHERALS
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7023 provides up to 20 general-purpose, bidirectional
I/O (GPIO) pins. All I/O pins apart from the pins shared with the
ADC are 5 V tolerant, meaning the GPIOs support an input voltage
of 5 V. The shared ADC pins only support an input up to AVDD.
In general, many of the GPIO pins have multiple functions (see
Table 55 for the pin function definitions). By default, the GPIO
pins are configured in GPIO mode.
All GPIO pins have an internal pull-up resistor (of about 100 kΩ)
and their drive capability is 1.6 mA. Note that a maximum of
20 GPIOs can drive 1.6 mA at the same time. Using the GPxPAR
registers, it is possible to enable/disable the pull-up resistors.
The 20 GPIOs are grouped in three ports, Port 0 to Port 2 (Port x).
Each port is controlled by four or five MMRs.
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a mode
other than GPIO. The PLA input is always active.
When the ADuC7023 part enters a power-saving mode, the
GPIO pins retain their state. Also note, that by setting RSTCFG
bit 0, the GPIO pins can retain their state during a watchdog or
software reset.
Table 55. GPIO Pin Function Descriptions
Configuration
Port
Pin
00
01
10
11
0
P0.0
GPIO/BM
nTRST
ADCBUSY
PLAI[8]
GPIO
TDO
PLAI[9]
GPIO
TDI
PLAO[8]
GPIO
TCK
PLAO[9]
P0.4
GPIO/IRQ0
SCL0
CONVSTART
PLAI[0]
P0.5
GPIO
SDA0
COMPOUT
PLAI[1]
P0.6
GPIO
MISO
PLAI[2]
P0.7
GPIO
MOSI
SDA12
PLAO[0]
1
P1.0
GPIO
SCLK
PWM0
PLAO[1]
P1.1
GPIO/IRQ1
SS
PWM1
PLAO[2]
GPIO/IRQ2
ADC4
ECLK
PLAI[3]
P1.3
GPIO/IRQ3
ADC5
PLAI[4]
P1.4
GPIO
ADC10
PLAO[3]
P1.5
GPIO
ADC6
PWMTRIPINPUT
PLAO[4]
P1.6
GPIO
PWM2
PLAI[5]
P1.7
GPIO
SDA14
PWM3
PLAI[6]
2
P2.0
GPIO
ADC12
PWM4
PLAI[7]
P2.2
GPIO
ADC7
PWMsync
PLAO[6]
P2.3
GPIO
ADC8
PLAO[7]
P2.4
GPIO
ADC9
PLAI[10]
1 These pins should not be used by user code when debugging the part via
JTAG. See Table 36 for further details on how to configure these pins for
GPIO mode. The default value of these pins depends on the level of the
P0.0/BM pin during the last reset sequence.
2 I2C1 function is only available on the 32-lead and 36-ball packages.
3 When configured in Mode 2, P1.2 is ECLK by default, or core clock output. To
configure it as a clock input, the MDCLK bits in PLLCON must be set to 11.
4 I2C1 function is only available on the 40-lead package.
GPxCON Registers
Name
Address
Default Value
Access
GP0CON
0xFFFFF400
0x00001111
R/W
GP1CON
0xFFFFF404
0x00000000
R/W
GP2CON
0xFFFFF408
0x00000000
R/W
GPxCON are the Port x control registers, which select the
function of each pin of Port x as described in Table 56.
Table 56. GPxCON MMR Bit Descriptions
Bit
Description
31 to 30
Reserved.
29 to 28
Select function of Px.7 pin.
27 to 26
Reserved.
25 to 24
Select function of Px.6 pin.
23 to 22
Reserved.
21 to 20
Select function of Px.5 pin.
19 to 18
Reserved.
17 to 16
Select function of Px.4 pin.
15 to 14
Reserved.
13 to 12
Select function of Px.3 pin.
11 to 10
Reserved.
9 to 8
Select function of Px.2 pin.
7 to 6
Reserved.
5 to 4
Select function of Px.1 pin.
3 to 2
Reserved.
1 to 0
Select function of Px.0 pin.
GP0PAR Register
Name
GP0PAR
Address
0xFFFFF42C
Default value
0x22220000
Access
Read/write
Function
GP0PAR programs the parameters for Port 0,
Port 1, and Port 2. Note that the GP0DAT
MMR must always be written after changing
the GP0PAR MMR.
GP1PAR Register
Name
GP1PAR
Address
0xFFFFF43C
Default value
0x22000022
Access
Read/write
Function
GP1PAR programs the parameters for Port 0,
Port 1, and Port 2. Note that the GP1DAT
MMR must always be written after changing
the GP1PAR MMR.
Rev. E
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