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| 型号： | EVAL-ADUC7126QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 89/108页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7126 |
| 设计资源： | EVAL-ADUC7126 Schematic ADUC7126 Gerber Files |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7126 |
| 所含物品： | 板 |
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Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 81 of 108
PROGRAMMABLE LOGIC ARRAY (PLA)
Every ADuC7124/ADuC7126 integrates a fully programmable
logic array (PLA) that consists of two independent but
interconnected PLA blocks. Each block consists of eight PLA
elements, giving each part a total of 16 PLA elements.
Each PLA element contains a two-input look up table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 51.
09
12
3-
1
33
4
2
0
1
3
A
B
LOOK-UP
TABLE
Figure 51. PLA Element
In total, 40 GPIO pins are available on the ADuC7124/ADuC7126
for the PLA. These include 16 input pins and 16 output pins that
must be configured in the GPxCON register as PLA pins before
using the PLA. Note that the comparator output is also included
as one of the 16 input pins.
The PLA is configured via a set of user MMRs. The output(s) of
the PLA can be routed to the internal interrupt system, to the
CONVSTART signal of the ADC, to an MMR, or to any of the 16
PLA output pins.
The two blocks can be interconnected as follows:
Output of Element 15 (Block 1) can be fed back to Input 0 of
Mux 0 of Element 0 (Block 0).
Output of Element 7 (Block 0) can be fed back to Input 0 of
Mux 0 of Element 8 (Block 1).
Table 117. Element Input/Output1
PLA Block 0
PLA Block 1
Element
Input
Output
Element
Input
Output
0
P1.0
P1.7
8
P3.0
P4.0
1
P1.1
P0.4
9
P3.1
P4.1
2
P1.2
P0.5
10
P3.2
P4.2
3
P1.3
P0.6
11
P3.3
P4.3
4
P1.4
P0.7
12
P3.4
P4.4
5
P1.5
P2.0
13
P3.5
P4.5
6
P1.6
P2.1
14
P3.6
P4.6
7
P0.0
P2.2
15
P3.7
P4.7
1 Not all pins in this table are connected to external pins. However, they may
be routed internally via the PLA. See Table 122 for further details.
PLA MMRs Interface
The PLA peripheral interface consists of the 22 MMRs.
Table 118. PLAELMx Registers
Name
Address
Default Value
Access
PLAELM0
0xFFFF0B00
0x0000
R/W
PLAELM1
0xFFFF0B04
0x0000
R/W
PLAELM2
0xFFFF0B08
0x0000
R/W
PLAELM3
0xFFFF0B0C
0x0000
R/W
PLAELM4
0xFFFF0B10
0x0000
R/W
PLAELM5
0xFFFF0B14
0x0000
R/W
PLAELM6
0xFFFF0B18
0x0000
R/W
PLAELM7
0xFFFF0B1C
0x0000
R/W
PLAELM8
0xFFFF0B20
0x0000
R/W
PLAELM9
0xFFFF0B24
0x0000
R/W
PLAELM10
0xFFFF0B28
0x0000
R/W
PLAELM11
0xFFFF0B2C
0x0000
R/W
PLAELM12
0xFFFF0B30
0x0000
R/W
PLAELM13
0xFFFF0B34
0x0000
R/W
PLAELM14
0xFFFF0B38
0x0000
R/W
PLAELM15
0xFFFF0B3C
0x0000
R/W
The PLAELMx are Element 0 to Element 15 control registers.
They configure the input and output mux of each element,
select the function in the look up table, and bypass/use the flip-
Table 119. PLAELMx MMR Bit Descriptions
Bit
Value
Description
[31:11]
Reserved.
[10:9]
Mux 0 control (see Table 122).
[8:7]
Mux 1 control (see Table 122).
6
Mux 2 control.
Set by the user to select the output of Mux 0. Cleared
by the user to select the bit value from PLADIN.
5
Mux 3 control.
Set by the user to select the input pin of the particular
element.
Cleared by the user to select the output of Mux 1.
[4:1]
Look-up table control.
0000
0.
0001
NOR.
0010
B AND NOT A.
0011
NOT A.
0100
A AND NOT B.
0101
NOT B.
0110
EXOR.
0111
NAND.
1000
AND.
1001
EXNOR.
1010
B.
1011
NOT A OR B.
1100
A.
1101
A OR NOT B.
1110
OR.
1111
1.
0
Mux 4 control.
Set by the user to bypass the flip-flop.
Cleared by the user to select the flip-flop (cleared by
default).
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