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| 型号： | EVAL-ADUC7126QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/108页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7126 |
| 设计资源： | EVAL-ADUC7126 Schematic ADUC7126 Gerber Files |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7126 |
| 所含物品： | 板 |
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Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 101 of 108
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7124/ADuC7126 operational power supply voltage
range is 2.7 V to 3.6 V. Separate analog and digital power supply
pins (AVDD and IOVDD, respectively) allow AVDD to be kept
relatively free of noisy digital signals often present on the
system IOVDD line. In this mode, the part can also operate with
split supplies; that is, it can use different voltage levels for each
supply. For example, the system can be designed to operate
with an IOVDD voltage level of 3.3 V while the AVDD level can be
at 3 V or vice versa. A typical split supply configuration is
shown in Figure 62.
09
12
3-
0
44
ADuC7124/
ADuC7126
0.1F
ANALOG
SUPPLY
10F
AVDD
DACVDD
GNDREF
DACGND
AGND
IOVDD
IOGND
0.1F
+
–
DIGITAL
SUPPLY
10F
+
–
Figure 62. External Dual Supply Connections
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series resistor
and/or ferrite bead between AVDD and IOVDD and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 63. With this configuration, other analog circuitry
(such as op amps, voltage reference, or any other analog circuitry)
can be powered from the AVDD supply line as well.
0
91
23-
14
5
ADuC7124/
ADuC7126
0.1F
BEAD
AVDD
AGND
IOVDD
DGND
0.1F
DIGITAL SUPPLY
ANALOG SUPPLY
10F
+
–
Figure 63. External Single Supply Connections
Notice that in both Figure 62 and Figure 63, a large value (10 μF)
reservoir capacitor sits on IOVDD, and a separate 10 μF capacitor
sits on AVDD. In addition, local small-value (0.1 μF) capacitors are
located at each AVDD and IOVDD pin of the chip. As per standard
design practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are close to each AVDD pin with trace
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
Finally, note that the analog and digital ground pins on the
ADuC7124/ADuC7126 must be referenced to the same system
ground reference point at all times.
IOVDD Supply Sensitivity
The IOVDD supply is sensitive to high frequency noise because it
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature
ensures that no flash interface timings or ARM7TDMI timings
are violated.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise sources below
recommended.
ADuC7124/
ADuC7126
IOVDD
IOGND
0.1F
DIGITAL
SUPPLY
10F
+
–
1H
09
12
3-
08
7
Figure 64. Recommended IOVDD Supply Filter
Linear Voltage Regulator
The ADuC7124/ADuC7126 require a single 3.3 V supply, but
the core logic requires a 2.6 V supply. An on-chip linear
regulator generates the 2.6 V from IOVDD for the core logic. The
LVDD pin is the 2.6 V supply for the core logic. An external
compensation capacitor of 0.47 μF must be connected between
LVDD and DGND (as close as possible to these pins) to act as a
tank of charge as shown in Figure 65.
0
9123
-046
ADuC7124/
ADuC7126
0.47F
LVDD
DGND
Figure 65. Voltage Regulator Connections
The LVDD pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOVDD to help improve line regulation performance of the on-
chip voltage regulator.
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