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| 型号： | EVAL-ADUC7126QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 59/108页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7126 |
| 设计资源： | EVAL-ADUC7126 Schematic ADUC7126 Gerber Files |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 类型： | MCU |
| 适用于相关产品： | ADUC7126 |
| 所含物品： | 板 |
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ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 54 of 108
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON,
which is described in Table 69.
CMPCON Register
Name:
CMPCON
Address:
0xFFFF0444
Default Value:
0x0000
Access:
Read/write
Table 69. CMPCON MMR Bit Descriptions
Bit
Value
Name
Description
[15:11]
Reserved.
10
CMPEN
Comparator enable bit.
Set by the user to enable the
comparator.
Cleared by the user to disable the
comparator.
[9:8]
CMPIN
Comparator negative input select
bits.
00
AVDD/2.
01
ADC3 input.
10
DAC0 output.
11
Reserved.
[7:6]
CMPOC
Comparator output configuration
bits.
00
Reserved.
01
Reserved.
10
Output on CMPOUT.
11
IRQ.
5
CMPOL
Comparator output logic state bit.
When low, the comparator output
is high if the positive input
(CMP0) is above the negative
input (CMP1). When high, the
comparator output is high if the
positive input is below the
negative input.
[4:3]
CMPRES
Response time.
00
5 μs response time typical for
large signals (2.5 V differential).
17 μs response time typical for
small signals (0.65 mV
differential).
11
4 μs typical.
01/10
Reserved.
2
CMPHYST
Comparator hysteresis sit.
Set by user to have a hysteresis of
about 7.5 mV.
Cleared by user to have no
hysteresis.
Bit
Value
Name
Description
1
CMPORI
Comparator output rising edge
interrupt.
Set automatically when a rising
edge occurs on the monitored
voltage (CMP0).
Cleared by user by writing a 1 to
this bit.
0
CMPOFI
Comparator output falling edge
interrupt.
Set automatically when a falling
edge occurs on the monitored
voltage (CMP0).
Cleared by user.
OSCILLATOR AND PLL—POWER CONTROL
Clocking System
The ADuC7124/ADuC7126 integrate a 32.768 kHz ± 3% oscilla-
tor, a clock divider, and a PLL. The PLL locks onto a multiple
(1275) of the internal oscillator or an external 32.768 kHz crystal to
provide a stable 41.78 MHz clock (UCLK) for the system. To allow
power saving, the core can operate at this frequency or at binary
submultiples of it. The actual core operating frequency, UCLK/2CD,
is referred to as HCLK. The default core clock is the PLL clock
divided by 8 (CD = 3) or 5.22 MHz. The core clock frequency
can also come from an external clock on the ECLK pin as
shown in Figure 45. The core clock can be output on ECLK
when using an internal oscillator or external crystal.
Note that, when the ECLK pin is used to output the core clock,
the output signal is not buffered and is not suitable for use as a
clock source to an external device without an external buffer.
091
23-
126
*32.768kHz ±3%
AT POWER UP
41.78MHz
OCLK
32.768kHz
WATCHDOG
TIMER
INT. 32kHz*
OSCILLATOR
CRYSTAL
OSCILLATOR
WAKEUP
TIMER
MDCLK
HCLK
PLL
CORE
I2C
UCLK
ANALOG
PERIPHERALS
/2CD
CD
XCLKO
XCLKI
XCLK
ECLK
Figure 45. Clocking System
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
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