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| 型号： | W9751G6KB-25 |
| 厂商： | Winbond Electronics |
| 文件页数： | 9/87页 |
| 文件大小： | 0K |
| 描述： | IC DDR2 SDRAM 512MBIT 84WBGA |
| 标准包装： | 209 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 512M（32Mx16） |
| 速度： | 2.5ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 84-TFBGA |
| 供应商设备封装： | 84-WBGA（8x12.5） |
| 包装： | 托盘 |
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W9751G6KB
8. FUNCTIONAL DESCRIPTION
8.1
Power-up and Initialization Sequence
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures
other than those specified may result in undefined operation. The following sequence is required for
Power-up and Initialization.
1. Apply power and attempt to maintain CKE below 0.2 × V DDQ and ODT *1 at a LOW state (all other
inputs may be undefined.) Either one of the following sequence is required for Power-up.
A. The V DD voltage ramp time must be no greater than 200 mS from when V DD ramps from 300
mV to V DD min; and during the V DD voltage ramp, |V DD -V DDQ | ≤ 0.3 volts.
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V DD , V DDL and V DDQ are driven from a single power converter output
V TT is limited to 0.95V max
V REF *2 tracks V DDQ /2
V DDQ ≥ V REF must be met at all times
B. Voltage levels at I/Os and outputs must be less than V DDQ during voltage ramp time to avoid
DRAM latch-up. During the ramping of the supply voltages, V DD ≥ V DDL ≥ V DDQ must be
maintained and is applicable to both AC and DC levels until the ramping of the supply voltages
is complete.
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Apply V DD /V DDL *3 before or at the same time as V DDQ
Apply V DDQ *4 before or at the same time as V TT
V REF *2 tracks V DDQ /2
V DDQ ≥ V REF must be met at all times
Apply V TT
The V TT voltage ramp time from when V DDQ min is achieved on V DDQ to when V TT min is
achieved on V TT must be no greater than 500 mS
2. Start Clock and maintain stable condition for 200 μS (min.).
3. After stable power and clock (CLK, CLK ), apply NOP or Deselect and take CKE HIGH.
4. Wait minimum of 400 nS then issue precharge all command. NOP or Deselect applied during 400
nS period.
5. Issue an EMRS command to EMR (2). (To issue EMRS command to EMR (2), provide LOW to
BA0, HIGH to BA1.)
6. Issue an EMRS command to EMR (3). (To issue EMRS command to EMR (3), provide HIGH to
BA0 and BA1.)
7. Issue EMRS to enable DLL. (To issue DLL Enable command, provide LOW to A0, HIGH to BA0
and LOW to BA1. And A9=A8=A7=LOW must be used when issuing this command.)
8. Issue a Mode Register Set command for DLL reset. (To issue DLL Reset command, provide HIGH
to A8 and LOW to BA0 and BA1.)
9. Issue a precharge all command.
10. Issue 2 or more Auto Refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment).
If OCD calibration is not used, EMRS to EMR (1) to set OCD Calibration Default
(A9=A8=A7=HIGH)
followed by EMRS to EMR
(1) to exit OCD Calibration Mode
(A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
13. The DDR2 SDRAM is now ready for normal operation.
Publication Release Date: Sep. 03, 2012
-9-
Revision A04
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9751G6KB25A | 制造商:WINBOND 制造商全称:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle |
| W9751G6KB25I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 512MBIT 2.5NS BGA |
| W9751G6KB25K | 制造商:WINBOND 制造商全称:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle |
| W9751G6KB25TR | 制造商:Winbond Electronics Corp 功能描述:512M DDR2-800, X16 制造商:Winbond 功能描述:512M DDR2-800, X16 |
| W9751G6KB-3 | 制造商:WINBOND 制造商全称:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle |
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