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参数资料
| 型号： | W9751G6KB-25 |
| 厂商： | Winbond Electronics |
| 文件页数： | 4/87页 |
| 文件大小： | 0K |
| 描述： | IC DDR2 SDRAM 512MBIT 84WBGA |
| 标准包装： | 209 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 512M（32Mx16） |
| 速度： | 2.5ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 84-TFBGA |
| 供应商设备封装： | 84-WBGA（8x12.5） |
| 包装： | 托盘 |
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W9751G6KB
1. GENERAL DESCRIPTION
The W9751G6KB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words ? 4 banks ? 16 bits.
This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various
applications. W9751G6KB is sorted into the following speed grades: -18, -25, 25I, 25A, 25K and -3.
The -18 is compliant to the DDR2-1066 (7-7-7) specification. The -25, 25I, 25A and 25K grade parts
are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade
which is guaranteed to support -40°C ≤ T CASE ≤ 95°C). The -3 is compliant to the DDR2-667 (5-5-5)
specification.
The automotive grade parts temperature, if offered, has two simultaneous requirements: ambient
temperature (T A ) surrounding the device cannot be less than -40°C or greater than +95°C (for 25A),
+105°C (for 25K), and the case temperature (T CASE ) cannot be less than -40°C or greater than +95°C
(for 25A), +105°C (for 25K). JEDEC specifications require the refresh rate to double when T CASE
exceeds +85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT
resistance and the input/output impedance must be derated when T CASE is < 0°C or > +85°C.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
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Power Supply: V DD , V DDQ = 1.8 V ? 0.1V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8X12.5 mm 2 ), using Lead free materials with RoHS compliant
Publication Release Date: Sep. 03, 2012
-4-
Revision A04
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9751G6KB25A | 制造商:WINBOND 制造商全称:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle |
| W9751G6KB25I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 512MBIT 2.5NS BGA |
| W9751G6KB25K | 制造商:WINBOND 制造商全称:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle |
| W9751G6KB25TR | 制造商:Winbond Electronics Corp 功能描述:512M DDR2-800, X16 制造商:Winbond 功能描述:512M DDR2-800, X16 |
| W9751G6KB-3 | 制造商:WINBOND 制造商全称:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle |
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