参数资料
型号: LT3430IFE-1#PBF
厂商: Linear Technology
文件页数: 7/28页
文件大小: 0K
描述: IC REG BUCK ADJ 3A 16TSSOP
标准包装: 95
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.2 V ~ 54 V
输入电压: 5.5 V ~ 60 V
PWM 型: 电流模式
频率 - 开关: 100kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
产品目录页面: 1331 (CN2011-ZH PDF)
LT3430/LT3430-1
BLOCK DIAGRAM
The LT3430/LT3430-1 are constant frequency, current
mode buck converters. This means that there is an in-
ternal clock and two feedback loops that control the duty
cycle of the power switch. In addition to the normal error
ampli?er, there is a current sense ampli?er that monitors
switch current on a cycle-by-cycle basis. A switch cycle
starts with an oscillator pulse which sets the R S ?ip-?op
to turn the switch on. When switch current reaches a level
set by the inverting input of the comparator, the ?ip-?op
is reset and the switch turns off. Output voltage control is
obtained by using the output of the error ampli?er to set
the switch current trip point. This technique means that the
error ampli?er commands current to be delivered to the
output rather than voltage. A voltage fed system will have
low phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
V IN
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.
Most of the circuitry of the LT3430/LT3430-1 operates
from an internal 2.9V bias line. The bias regulator normally
draws power from the regulator input pin, but if the BIAS
pin is connected to an external voltage equal to or higher
than 3V, bias power will be drawn from the external source
(typically the regulated output voltage). This will improve
ef?ciency if the BIAS pin voltage is lower than regulator
input voltage.
High switch ef?ciency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external ca-
pacitor and diode. Two comparators are connected to the
shutdown pin. One has a 2.38V threshold for undervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.
3, 4
R LIMIT
R SENSE
BIAS 10
2.9V BIAS
REGULATOR
INTERNAL
V CC
CURRENT
SLOPE COMP
Σ
COMPARATOR
SYNC 14
ANTISLOPE COMP
BOOST
6
SHUTDOWN
COMPARATOR
200kHz: LT3430
0.4V
100kHz: LT3430-1
OSCILLATOR
S
R
R S
FLIP-FLOP
DRIVER
CIRCUITRY
Q1
POWER
SWITCH
5.5 μ A
SW
SHDN 15
+
LOCKOUT
COMPARATOR
× 1
Q2
FREQUENCY
FOLDBACK
2, 5
V C(MAX)
CLAMP
Q3
FOLDBACK
CURRENT
LIMIT
CLAMP
ERROR
AMPLIFIER
g m = 2000 μ Mho
12 FB
2.38V
11
V C
1.22V
GND
1, 8, 9, 16, 17
3430 F01
Figure 1. LT3430/LT3430-1 Block Diagram
34301fa
7
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