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| 型号： | LT3430IFE-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A 16TSSOP |
| 标准包装： | 95 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.2 V ~ 54 V |
| 输入电压： | 5.5 V ~ 60 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 100kHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 16-TSSOP-EP |
| 产品目录页面： | 1331 (CN2011-ZH PDF) |
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LT3430/LT3430-1
APPLICATIONS INFORMATION
R FB
LT3430/LTC3430-1
L1
INPUT
IN
2.38V
+
V SW
OUTPUT
STANDBY
R HI
5.5 μ A
–
SHDN
+
TOTAL
SHUTDOWN
+
C1
C2
R LO
0.4V
–
GND
3430 F04
Figure 4. Undervoltage Lockout
R LO [ IN ? 2 . 38 ( ? V / V OUT + 1 ) + ? V ]
2 . 38 ? R LO ( )
5 . 5 μ A
[
]
25 k 12 ? 2 . 38 ( 1 . 5 / 5 + 1 ) + 1 . 5
2 . 38 – 25 k ( )
5 . 5 μ A
25 k ( )
=
= 116 k
V
R HI =
R FB = ( R HI ) ( V OUT / ? V )
25k suggested for R LO
V IN = Input voltage at which switching stops as input
voltage descends to trip level
?V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if
input voltage drops below 12V and should not restart
unless input rises back to 13.5V. ?V is therefore 1.5V and
V IN = 12V. Let R LO = 25k.
R HI =
10 . 41
2 . 24
R FB = 116 k ( 5 / 1 . 5 ) = 387 k
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The LT3430 synchronizing range
is equal to initial operating frequency up to 700kHz. This
means that minimum practical sync frequency is equal to
the worst-case high self-oscillating frequency (228kHz), not
the typical operating frequency of 200kHz. Caution should
be used when synchronizing above 265kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insuf?cient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation. The LT3430-1 synchronizing range
is from 125kHz to 250kHz (slope compensation loss oc-
curs above 133kHz).
At power-up, when V C is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows
the frequency foldback to operate in the shorted output
condition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
34301fa
16
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| LT3431EFE#PBF | 功能描述:IC REG BUCK ADJ 3A 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
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