参数资料
型号: LT3430IFE-1#PBF
厂商: Linear Technology
文件页数: 22/28页
文件大小: 0K
描述: IC REG BUCK ADJ 3A 16TSSOP
标准包装: 95
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.2 V ~ 54 V
输入电压: 5.5 V ~ 60 V
PWM 型: 电流模式
频率 - 开关: 100kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
产品目录页面: 1331 (CN2011-ZH PDF)
LT3430/LT3430-1
APPLICATIONS INFORMATION
stability. This ESR, however, contributes signi?cantly to
the ripple voltage at the output (see Output Ripple Voltage
in the Applications Information section). It is possible to
reduce capacitor size and output ripple voltage by replac-
ing the tantalum output capacitor with a ceramic output
capacitor because of its very low ESR. The zero provided
by the tantalum output capacitor must now be reinserted
back into the loop. Alternatively, there may be cases where,
even with the tantalum output capacitor, an additional
zero is required in the loop to increase phase margin for
improved transient response.
A zero can be added into the loop by placing a resistor (R C )
at the V C pin in series with the compensation capacitor,
C C , or by placing a capacitor (C FB ) between the output
and the FB pin.
When using R C , the maximum value has two limitations.
First, the combination of output capacitor ESR and R C
may stop the loop rolling off altogether. Second, if the
loop gain is not rolled off suf?ciently at the switching
frequency, output ripple will perturb the V C pin enough to
cause unstable duty cycle switching similar to subharmonic
oscillations. If needed, an additional capacitor (C F ) can be
added across the R C /C C network from the V C pin to ground
to further suppress V C ripple voltage.
With a tantalum output capacitor, the LT3430/LT3430-1
already includes a resistor (R C ) and ?lter capacitor (C F )
at the V C pin (see Figures 10 and 11) to compensate the
loop over the entire V IN range (to allow for stable pulse
skipping for high V IN -to-V OUT ratios ≥ 10). A ceramic output
capacitor can still be used with a simple adjustment to the
resistor R C for stable operation (see Ceramic Capacitors
section for stabilizing LT3430). If additional phase margin
is required, a capacitor (C FB ) can be inserted between the
output and FB pin but care must be taken for high output
voltage applications. Sudden shorts to the output can create
unacceptably large negative transients on the FB pin.
For V IN -to-V OUT ratios < 10, higher loop bandwidths are
possible by readjusting the frequency compensation
components at the V C pin.
When checking loop stability, the circuit should be operated
over the application’s full voltage, current and tempera-
ture range. Proper loop compensation may be obtained
by empirical methods as described in Application Notes
19 and 76.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for example,
a battery powered device with a wall adapter input, the
output of the LT3430/LT3430-1 can be held up by the
backup supply with the LT3430/LT3430-1 input discon-
nected. In this condition, the SW pin will source current
into the V IN pin. If the ? S ? H ? D ? N pin is held at ground, only the
shut down current of 30μA will be pulled via the SW pin
from the second supply. With the ? S ? H ? D ? N pin ?oating, the
LT3430/LTC3430-1
80
60
180
150
CURRENT MODE
POWER STAGE
g m = 2mho
ERROR
AMPLIFIER
V SW
C FB
R1
OUTPUT
40
GAIN
120
FB
TANTALUM CERAMIC
20
90
R O
200k
g m =
2000 μ mho
1.22V
R LOAD
+
ESR
ESL
0
PHASE
60
GND
V C
C1
C1
–20
30
R C
C F
R2
–40
10
100
1k 10k
FREQUENCY (Hz)
100k
0
1M
3430 F11
C C
3430 F10
V IN = 42V
V OUT = 5V
I LOAD = 1A
C OUT = 100 μ F, 10V, 0.1 ?
R C = 3.3k
C C = 22nF
C F = 220pF
Figure 10. Model for Loop Response
Figure 11. Overall Loop Response
34301fa
22
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