参数资料
| 型号： | 71M6541F-DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 78/166页 |
| 文件大小： | 0K |
| 描述： | DEMO BOARD 71M6541F |
| 标准包装： | 1 |
| 系列： | * |
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71M6541D/F/G and 71M6542F/G Data Sheet
SFM Details
The following occurs upon entering SFM.
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The CE is disabled.
The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be
accomplished with the RESET pin, a watchdog reset, or by cycling power (without battery at the
VBAT pin).
The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase
cycle.
Mass erase is invoked if specified in the SFMM register, I/O RAM 0x2080 (see Invoking SFM, above).
The SECURE bit ( SFR 0xB2[6] ) is cleared at the end of this and all Mass Erase cycles.
All SPI read and write operations now refer to Flash instead of XRAM space.
The SPI host can access the current state of the pending multi-cycle Flash access by performing a 4-byte
SPI write of any address and checking the status field.
All SPI write operations in SFM mode must be 6-byte write transaction that writes two bytes to an even
address. The write transactions must contain a command byte of the form 0xxx xxxx. Auto incrementing
is disabled for write operations.
SPI read transactions can make use of auto increment and may access single bytes. The command byte
must always be of the form 1xxx xxxx in SFM read transactions.
SPI commands in SFM
Interrupts are not generated in SFM since the MPU is halted. The format of the commands is described in
2.5.11 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6541D/F/G and
71M6542F/G. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU
firmware at least every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is
reset as if the RESET pin were pulled high, except that the I/O RAM bits are in the same state as after a
for a list of I/O RAM bit states after RESET and wake-up). After 4100 CK32 cycles (or 125 ms) following
the WDT overflow, the MPU is launched from program address 0x0000.
The watchdog timer is also reset when the internal signal WAKE=0 (see 3.4 Wake Up Behavior ).
2.5.12 Test Ports (TMUXOUT and TMUX2OUT Pins)
Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT
and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function
as test pins, LCD_MAP[46] ( I/O RAM 0x2406[6]) and LCD_MAP[47] ( I/O RAM 0x2406[7] ) must be 0.
One of the digital or analog signals listed in
Table 65 can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled
with the I/O RAM register TMUX[5:0] (I/O RAM 0x2502[5:0] , as shown in
One of the digital or analog signals listed in Table 66 can be selected to be output on the TMUX2OUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]) , as
The TMUX[5:0] and TMUX2[4:0] I/O RAM locations are non-volatile and their contents are preserved
by battery power and across resets.
78
Rev 4
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| 72346-001 | 72346-1-SCA-II REC |
| 72347-001LF | CONN RECEPT SCA2 20POS VERT PCB |
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相关代理商/技术参数 |
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| 71M6541F-IGT/F | 功能描述:计量片上系统 - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6541F-IGTR/F | 功能描述:计量片上系统 - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6541FT-IGT/F | 制造商:Maxim Integrated Products 功能描述:1-PHASE SOC, 64KB FLASH, PRES TEMP SENSOR - Rail/Tube |
| 71M6541FT-IGTR/F | 制造商:Maxim Integrated Products 功能描述:1-PHASE SOC, 64KB FLASH, PRES TEMP SENSOR - Tape and Reel |
| 71M6541G | 制造商:未知厂家 制造商全称:未知厂家 功能描述:71M6541D/71M6541F/71M6541G/71M6542F/71M6542G 是 TeridianTM 的第4 代高集成度单相电表SoC |
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