参数资料
型号: 71M6541F-DB
厂商: Maxim Integrated Products
文件页数: 129/166页
文件大小: 0K
描述: DEMO BOARD 71M6541F
标准包装: 1
系列: *
71M6541D/F/G and 71M6542F/G Data Sheet
status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in
CESTATUS is shown in Table 81 .
Table 81: CESTATUS ( CE RAM 0x80 ) Bit Definitions
CESTATUS
bit
31:4
3
2
1
0
Name
Not Used
F0
Not Used
SAG_B
SAG_A
Description
These unused bits are always zero.
F0 is a square wave at the exact fundamental input frequency.
This unused bit is always zero.
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VB rises above
SAG_THR .
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VA rises above
SAG_THR .
The CE is initialized by the MPU using CECONFIG ( Table 82 ). This register contains in packed form
SAG_CNT, FREQSEL[1:0], EXT_PULSE, PULSE_SLOW and PULSE_FAST . The CECONFIG bit definitions are
given in Table 83 .
Table 82: CECONFIG Register
0x0030DB00
CE
Address
0x20
Name
CECONFIG
Data
1
0x00B0DB00 2
Description
See description of the CECONFIG bits in
1. Default for CE41A01 (71M6541D/F/G or CE41A04 (71M6542F/G) CE code for use with local
sensors.
2. Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote
sensors.
Table 83: CECONFIG ( CE RAM 0x20 ) Bit Definitions
CECONFIG
bit
Name
Default Description
23
Reserved
0
Reserved (can be used by the MPU to indicate that the
71M6x01 is being used; CE does not use this).
When 1, the MPU controls temperature compensation via the
22
EXT_TEMP
0
GAIN_ADJn registers ( CE RAM 0x40-0x42) , when 0, the CE is in
control.
When 1, XPULSE produces a pulse for each zero-crossing of
21
EDGE_INT
1
the mains phase selected by FREQSEL[1:0] , which can be used
to interrupt the MPU.
20
19:8
SAG_INT
SAG_CNT
1
252
(0xFC)
When 1, activates YPULSE output when a sag condition is
detected.
The number of consecutive voltage samples below SAG_THR
(CE RAM 0x24 ) before a sag alarm is declared. The default value
is equivalent to 100 ms.
FREQSEL[1:0] selects the phase to be used for the frequency
monitor, sag detection, and for the zero crossing counter
( MAINEDGE_X, CE RAM 0x83 ).
7:6
FREQSEL[1:0]
0
FREQ SEL[1:0]
0
0
0
1
1
X
Phase Selected
A
B*
Not allowed
*71M6542F/G only
Rev 4
129
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