参数资料
型号: 71M6541F-DB
厂商: Maxim Integrated Products
文件页数: 120/166页
文件大小: 0K
描述: DEMO BOARD 71M6541F
标准包装: 1
系列: *
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
Rst Wk Dir
Description
OPT_RXINV
2457[1]
0
R/W
Inverts result from OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
Configures the OPT_TX output pin.
If LCD_MAP[51] = 0:
OPT_TXE [1:0]
2456[3:2]
00 –
R/W
00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VARPULSE
If LCD_MAP[51] = 1:
xx = SEG51
OPT_TXINV
2456[0]
0
R/W
Invert OPT_TX when 1. This inversion occurs before modulation.
Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is
OPT_TXMOD
2456[1]
0
R/W
modulated when it would otherwise have been zero. The modulation is applied
after any inversion caused by OPT_TXINV .
OSC_COMP
PB_STATE
PERR_RD
PERR_WR
PLL_OK
28A0[5]
SFR F8[0]
SFR FC[6]
SFR FC[5]
SFR F9[4]
0
0
0
0
0
0
0
R/W
R
R/W
R
Enables the automatic update of RTC_P and RTC_Q every time the temperature
is measured.
The de-bounced state of the PB pin.
The IC sets these bits to indicate that a parity error on the remote sensor has
been detected. Once set, the bits are remembered until they are cleared by
the MPU.
Indicates that the clock generation PLL is settled.
Controls the speed of the PLL and MCK.
PLL_FAST
2200[4]
0
0
R/W
1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going
pulse if PLS_INV =0 or high-going pulse if PLS_INV =1). The maximum pulse
PLS_MAXWIDTH[7:0]
210A[7:0]
FF FF R/W
width is (2* PLS_MAXWIDTH[7:0] + 1)*T I . Where T I is PLS_INTERVAL[7:0] in
units of CK_FIR clock cycles. If PLS_INTERVAL[7:0] = 0 or
PLS_MAXWIDTH[7:0] = 255, no pulse width checking is performed and the
output pulses have 50% duty cycle. See 2.3.6.2 VPULSE and WPULSE .
120
Rev 4
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