参数资料
型号: W9751G6IB-25
厂商: Winbond Electronics
文件页数: 52/86页
文件大小: 0K
描述: IC DDR2-800 SDRAM 512MB 84-WBGA
标准包装: 210
格式 - 存储器: RAM
存储器类型: DDR2 SDRAM
存储容量: 512M(32Mx16)
速度: 2.5ns
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: 0°C ~ 85°C
封装/外壳: 84-TFBGA
供应商设备封装: 84-WBGA(8x12.5)
包装: 托盘
W9751G6IB
tERR ( nper ) = ? ∑ tCK j ? – n × tCK ( avg )
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tJIT(duty)
tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from
tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg).
tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)}
where,
tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200}
tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200}
tJIT(per), tJIT(per,lck)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.
tJIT(cc), tJIT(cc,lck)
tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles:
tJIT(cc) = Max of |tCKi+1 – tCKi|
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.
tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)
tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).
? i + n ? 1 ?
? j = 1 ?
?
?
Where ?
?
? ? 11 ≤ n ≤ 50
? n = 2
n = 3
? n = 4
n = 5
? 6 ≤ n ≤ 10
?
for tER R(2per)
for tER R(3per)
for tER R(4per)
for tER R(5per)
for tER R(6 – 10per)
for tER R(11 – 50per)
Publication Release Date: Oct. 23, 2009
- 52 -
Revision A06
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