- 您现在的位置：买卖IC网 > Datasheet目录369 > W9751G6IB-25 (Winbond Electronics)IC DDR2-800 SDRAM 512MB 84-WBGA Datasheet资料下载
参数资料
| 型号： | W9751G6IB-25 |
| 厂商： | Winbond Electronics |
| 文件页数： | 3/86页 |
| 文件大小： | 0K |
| 描述： | IC DDR2-800 SDRAM 512MB 84-WBGA |
| 标准包装： | 210 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 512M（32Mx16） |
| 速度： | 2.5ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 84-TFBGA |
| 供应商设备封装： | 84-WBGA（8x12.5） |
| 包装： | 托盘 |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页
W9751G6IB
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
10.21
10.22
10.23
10.24
10.25
Command Input Timing.......................................................................................................................67
Timing of the CLK Signals...................................................................................................................67
ODT Timing for Active/Standby Mode.................................................................................................68
ODT Timing for Power Down Mode ....................................................................................................68
ODT Timing mode switch at entering power down mode ....................................................................69
ODT Timing mode switch at exiting power down mode ......................................................................70
Data output (read) timing ....................................................................................................................71
Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................71
Data input (write) timing ......................................................................................................................72
Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4)...........................................................72
Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ......................................73
Seamless burst write operation: RL = 5 ( WL = 4, BL = 4).........................................................73
Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) .............................................................74
Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) ..................................................74
Write operation with Data Mask: WL=3, AL=0, BL=4) ...............................................................75
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≦ 2clks) .............76
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≦ 2clks) .............76
Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≦ 2clks) .............77
Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≦ 2clks) .............77
Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP>2clks) ..............78
Burst write operation followed by precharge: WL = (RL-1) = 3 ..................................................78
Burst write operation followed by precharge: WL = (RL-1) = 4 ..................................................79
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≦ 2clks)................79
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP>2clks) .................80
Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≦ 2clks) .......................................................................................80
10.26
Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≦ 2clks) .......................................................................................81
11.
10.27
10.28
10.29
10.30
10.31
10.32
Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3.................................81
Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 .......................82
Self Refresh Timing ...................................................................................................................82
Active Power Down Mode Entry and Exit Timing.......................................................................83
Precharged Power Down Mode Entry and Exit Timing ..............................................................83
Clock frequency change in precharge Power Down mode ........................................................84
PACKAGE SPECIFICATION ..............................................................................................................85
Package Outline WBGA-84 (10x12.5 mm 2 ).....................................................................................................85
12.
REVISION HISTORY ..........................................................................................................................86
Publication Release Date: Oct. 23, 2009
-3-
Revision A06
相关PDF资料 |
PDF描述 |
|---|---|
| W9751G6KB-25 | IC DDR2 SDRAM 512MBIT 84WBGA |
| W9812G6JH-6I | IC SDRAM 128MBIT 54TSOPII |
| W9816G6IH-6I | IC SDRAM 16MBIT 50TSOPII |
| W9825G6JH-6I | IC SDRAM 256MBIT 54TSOPII |
| W9864G6JH-6I | IC SDRAM 64MBIT 54TSOPII |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W9751G6JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6JB-25 | 制造商:Winbond Electronics Corp 功能描述:512GB DDRII |
| W9751G6JB-3 | 制造商:Winbond Electronics Corp 功能描述:512MB DDRII |
| W9751G6KB | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6KB-18 | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
发布紧急采购，3分钟左右您将得到回复。