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参数资料
| 型号： | W9751G6IB-25 |
| 厂商： | Winbond Electronics |
| 文件页数： | 4/86页 |
| 文件大小： | 0K |
| 描述： | IC DDR2-800 SDRAM 512MB 84-WBGA |
| 标准包装： | 210 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 512M（32Mx16） |
| 速度： | 2.5ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 84-TFBGA |
| 供应商设备封装： | 84-WBGA（8x12.5） |
| 包装： | 托盘 |
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W9751G6IB
1. GENERAL DESCRIPTION
The W9751G6IB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words × 4 banks × 16 bits.
This device achieves high speed transfer rates up to 800Mb/sec/pin (DDR2-800) for general
applications. W9751G6IB is sorted into the following speed grades: 25F, -25 and -3. The 25F is
compliant to the DDR2-800 (5-5-5) specification. The -25 is compliant to the DDR2-800 (6-6-6)
specification. The -3 is compliant to the DDR2-667 (5-5-5) specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single-ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
Power Supply: V DD , V DDQ = 1.8 V ± 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5 and 6
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data.
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (10X12.5 mm 2 ), using Lead free materials with RoHS compliant
Publication Release Date: Oct. 23, 2009
-4-
Revision A06
相关PDF资料 |
PDF描述 |
|---|---|
| W9751G6KB-25 | IC DDR2 SDRAM 512MBIT 84WBGA |
| W9812G6JH-6I | IC SDRAM 128MBIT 54TSOPII |
| W9816G6IH-6I | IC SDRAM 16MBIT 50TSOPII |
| W9825G6JH-6I | IC SDRAM 256MBIT 54TSOPII |
| W9864G6JH-6I | IC SDRAM 64MBIT 54TSOPII |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W9751G6JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6JB-25 | 制造商:Winbond Electronics Corp 功能描述:512GB DDRII |
| W9751G6JB-3 | 制造商:Winbond Electronics Corp 功能描述:512MB DDRII |
| W9751G6KB | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6KB-18 | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
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