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参数资料
| 型号： | A8582KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 23/32页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 16TSSOP |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.7 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 250kHz ~ 2.45MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-TSSOP-EP |
| 其它名称： | 620-1395-6 |
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A8582
A Generalized Tuning Procedure
Wide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
4) Calculate the CZ capacitor value by setting f Z2 at 1.5 × f P1 :
1) Choose the system bandwidth, f C , the frequency at which the
magnitude of the gain will cross 0 dB. Recommended values for
C Z =
2×
1
× R Z × 1.5 × f P1
(26)
2 × ESR × C OUT
R Z = f C × ×
V OUT 2× × C OUT
V FB
g mPOWER × g m
2 × R LOAD × C OUT
f C based on the PWM switching frequency are: f SW /20 < f C <
f SW /10. A higher value of f C will generally provide a better tran-
sient response, while a lower value of f C will be easier to obtain
higher gain and phase margins.
2) Calculate the RZ resistor value to set the required system
bandwidth (f C ):
(25)
3) Determine the frequency of the pole (f P1 ) formed by C OUT and
R LOAD by using equation 19 (repeated here):
1
f P1 =
75
5) Calculate the frequency of the ESR zero (f Z1 ) formed by the
output capacitor(s) by using equation 20 (repeated here):
1
f Z1 = (20)
5a) If f Z1 is at least 1 decade higher than the target crossover fre-
quency (f C ) then f Z1 can be ignored. This is usually the case
for a design using ceramic output capacitors. Use equation 24
to calculate the value of CP by setting f P3 to either 10 × f C or
f SW / 2, whichever is higher.
5b) On the other hand, if f Z1 is near or below the target crossover
frequency (f C ) then use equation 24 to calculate the value of
CP by setting f P3 equal to f Z1 . This is usually the case for a
design using high ESR electrolytic output capacitors.
75
50
G C = 45.6 dB
50
f C = 135 kHz
25
0
-25
-50
180
90
f P2 = 183 Hz
f Z2 = 13.2 kHz
f P3 = 1.0 MHz
25
0
-25
-50
180
90
Combined
P hase Margin = 82°
0
0
Combined
-90
10 1
10 2
10 3
10 4
10 5
10 6
10 7
-90
10 1
10 2
10 3
10 4
10 5
10 6
10 7
Frequency (Hz)
Figure 16. Compensated Error amplifier Bode plot
Frequency (Hz)
Figure 17. Bode plot for the complete system (combined = red curve)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23
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| A8583KLPTR-T | 功能描述:IC REG BUCK ADJ 3.5A 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:50 系列:- 类型:升压（升压） 输出类型:可调式 输出数:1 输出电压:5 V ~ 25 V 输入电压:2.3 V ~ 5.5 V PWM 型:电流模式 频率 - 开关:600kHz，1.2MHz 电流 - 输出:1A 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装:管件 供应商设备封装:8-MSOP |
| A8584 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:The A8584 is an adjustable frequency, high output current, PWM regulator that integrates a low resistance, high-side, N-channel MOSFET. |
| A8584KLPTR-T | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:The A8584 is an adjustable frequency, high output current, PWM regulator that integrates a low resistance, high-side, N-channel MOSFET. |
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