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| 型号： | A8582KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 16TSSOP |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.7 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 250kHz ~ 2.45MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-TSSOP-EP |
| 其它名称： | 620-1395-6 |
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A8582
Sleep Mode
If the voltage at the EN/SYNC pin is pulled below 400 mV
(V ENILSLEEP ) the A8582 will enter a sleep mode where the inter-
nal control circuits will be shut off and draw less than 3 μ A from
V IN . However, the total current drawn by the VIN pin will be the
sum of the current drawn by the control circuitry (<3 μ A) plus
any leakage due to the high-side MOSFET (<10 μ A at 25°C).
Enable/Synchronization (EN/SYNC) Input
The enable/synchronization (EN/SYNC) input provides three
functions:
? A control input that commands the sleep mode of the A8582.
When EN/SYNC is very low (V EN/SYNC < V ENILSLEEP ), most
of the internal circuits are de-biased to provide the sleep mode
current of less than 3 μ A.
Wide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
Note that, when used as a synchronization input, soft start is at
the base frequency set by the FSET resistor. Synchronization
to the external clock occurs after soft start is completed (when
V FB > V POKTHRESH ). When being used as a synchronization
input, the applied clock pulses must satisfy the pulse width, duty-
cycle, and rise/fall time requirements shown in the Electrical
Characteristics table in this datasheet.
To automatically enable the A8582, the EN/SYNC input pin may
be connected to a voltage rail, such as V IN , via a resistor and a
Zener diode as shown in figure 4.
There is a short delay between when EN/SYNC transitions low
and when PWM switching stops. This is necessary because the
enable circuitry must distinguish between a constant logic level
and synchronization pulses at the lowest switching frequency.
The nominal delay from when EN/SYNC transitions low and
PWM switching stopping is 32 PWM clock cycles. The shut-
? A simple logic input. If EN/SYNC is a logic low (V EN/SYNC <
V ENIL ), then the A8582 and VOUT will be off. If EN/SYNC is
a logic high (V EN/SYNC > V ENIH ), the A8582 will turn on and,
provided there are no fault conditions, soft start will be initiated
and VOUT will ramp to its final voltage in a time set by the soft
start capacitor (CSS). (The operating modes of the A8582 based
R
V IN
EN/SYNC
A8582
on EN/SYNC voltage are summarized in figure 3.)
? A synchronization input that accepts an external clock to turn on
the A8582 and (after soft starting) will scale the PWM switch-
ing frequency from 1.2X to 1.5X above the base frequency set
by the FSET resistor.
V EN > 1.15 V
2.2 V < V Z < 4.7 V
Figure 4. Automatically enabling the A8582 from VIN or some other
power rail
V EN > 1.65 V
SLEEP
(i IN < 3 μ A
PWM = Off )
V SS < 0.2 V
Discharge
Soft-start capacitor
(PWM = Off)
V EN < 0.85 V
for 32 cycles
WAKE
(i IN ≈ 2 mA
PWM = Off )
Wait up to
32 cycles
(PWM = On)
V EN > 1.15 V
RUN
(i IN ≈ 3 mA
PWM = On )
V EN < 0.85 V
Timer expired
Figure 3. EN/SYNC voltage and A8582 operating modes
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
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| A8583KLPTR-T | 功能描述:IC REG BUCK ADJ 3.5A 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:50 系列:- 类型:升压（升压） 输出类型:可调式 输出数:1 输出电压:5 V ~ 25 V 输入电压:2.3 V ~ 5.5 V PWM 型:电流模式 频率 - 开关:600kHz，1.2MHz 电流 - 输出:1A 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装:管件 供应商设备封装:8-MSOP |
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