参数资料
型号: A8582KLPTR-T
厂商: Allegro Microsystems Inc
文件页数: 16/32页
文件大小: 0K
描述: IC REG BUCK ADJ 2A 16TSSOP
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 可调至 0.8V
输入电压: 4.7 V ~ 36 V
PWM 型: 电流模式
频率 - 开关: 250kHz ~ 2.45MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 标准包装
供应商设备封装: 16-TSSOP-EP
其它名称: 620-1395-6
A8582
Wide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
Application Information
R FSET = 26730 – 1.8
Design and Component Selection
f SW
(2)
R FB2 = 0.8 V – 1
R FB1 V OUT
V OUT
(V)
Setting the Output Voltage (VOUT, RFB1, RFB2)
The output voltage of the A8582 is determined by connecting
a resistor divider from the output node (VOUT) to the FB pin,
as shown in figure 10. There are trade-offs when choosing the
value of the feedback resisters. If the series combination (RFB1
+ RFB2) is relatively low, the light load efficiency of the regula-
tor will be reduced. So to maximize the efficiency, it is best to
choose high values for the resistors. On the other hand, if the par-
allel combination (RFB1 // RFB2) is too high, then the regulator
may be susceptible to noise coupling into the FB pin. In general,
the feedback resisters must satisfy the ratio shown in equation 1
to produce a required output voltage.
(1)
When the PWM switching frequency is chosen, the designer
should be aware of the minimum controllable PWM on-time,
t ON(MIN) of the A8582. If the system required on-time is less than
the A8582 minimum controllable on-time, then switch node jitter
will occur, and the output voltage will have increased ripple or
oscillations. The PWM switching frequency should be calculated
using equation 3, where V OUT is the output voltage, t ON(MIN) is
the minimum controllable on-time of the A8582 (worst case of
Table 2. Recommended Feedback Resistor Values
RFB1 RFB2
VOUT to FB pin FB pin to GND
(k Ω ) (k Ω )
1.2 6.04 12.1
Table 2 shows the most common output voltages and recom-
mended feedback resistor values, assuming less than 0.2% effi-
ciency loss at light load of 100 mA and a parallel combination of
4 k Ω presented to the FB pin. For optimal system accuracy, it is
recommended that the feedback resistors have ≤ 1% tolerances.
PWM Switching Frequency (RFSET)
1.5
1.8
2.5
3.3
5.0
7.0
8.0
9.6
7.50
9.09
12.4
16.5
24.9
34.8
40.2
47.5
8.45
7.15
5.76
5.23
4.75
4.53
4.42
4.32
The PWM switching frequency is set by connecting a resistor
from the FSET pin to ground. Figure 11 is a graph showing the
relationship between the typical switching frequency (y axis)
and the FSET resistor, 1/R FSET (x axis). For a given switching
frequency (f SW ), the FSET resistor can be calculated using equa-
tion 2, where f SW is in kHz and R FSET is in k Ω .
VOUT
2400
2200
2000
1800
1600
1400
1200
A8582
FB
RFB1
1000
800
600
400
RFB2
200
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0.11
1/ RFSET Resistance, 1/R FSET (k Ω )
Figure 10. Connecting the feedback divider
Figure 11. PWM switching frequency versus 1/R FSET
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
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